Searched refs:SSCR1_SP (Results 1 – 1 of 1) sorted by relevance
1071 #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ macro1072 #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */1074 #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */