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/external/llvm/test/CodeGen/X86/
Dvector-shuffle-sse1.ll2 ; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 | FileCheck %s --check-prefix=SSE1
7 ; SSE1-LABEL: shuffle_v4f32_0001:
8 ; SSE1: # BB#0:
9 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
10 ; SSE1-NEXT: retq
15 ; SSE1-LABEL: shuffle_v4f32_0020:
16 ; SSE1: # BB#0:
17 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
18 ; SSE1-NEXT: retq
23 ; SSE1-LABEL: shuffle_v4f32_0300:
[all …]
Dvec_fneg.ll2 …ple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1
4 …e=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE1
55 ; X32-SSE1-LABEL: fneg_bitcast:
56 ; X32-SSE1: # BB#0:
57 ; X32-SSE1-NEXT: pushl %ebp
58 ; X32-SSE1-NEXT: movl %esp, %ebp
59 ; X32-SSE1-NEXT: andl $-16, %esp
60 ; X32-SSE1-NEXT: subl $32, %esp
61 ; X32-SSE1-NEXT: movl $-2147483648, %eax # imm = 0x80000000
62 ; X32-SSE1-NEXT: movl 12(%ebp), %ecx
[all …]
Dmemcpy-2.ll3 …llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1
28 ; SSE1-LABEL: t1:
29 ; SSE1: movaps _.str, %xmm0
30 ; SSE1: movaps %xmm0
31 ; SSE1: movb $0, 24(%esp)
32 ; SSE1: movl $0, 20(%esp)
33 ; SSE1: movl $0, 16(%esp)
68 ; SSE1-LABEL: t2:
69 ; SSE1: movaps (%ecx), %xmm0
70 ; SSE1: movaps %xmm0, (%eax)
[all …]
Dmemset-sse-stack-realignment.ll5 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium3 | FileCheck %s -check-prefix=SSE1
21 ; SSE1-LABEL: test1:
22 ; SSE1: andl $-16
23 ; SSE1: movl %esp, %esi
24 ; SSE1: movaps
54 ; SSE1-LABEL: test2:
55 ; SSE1: andl $-16
56 ; SSE1: movl %esp, %esi
57 ; SSE1: movaps
Dsoft-fp.ll6 ; RUN: | FileCheck %s --check-prefix=SSE1 --check-prefix=CHECK
41 ; SSE1: xmm{{[0-9]+}}
54 ; SSE1: xmm{{[0-9]+}}
Dsse1.ll1 ; Tests for SSE1 and below, without SSE2+.
37 ; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
51 ; v4i32 isn't legal for SSE1, but this should be cmpps.
Dinline-sse.ll6 ; PR16133 - we must treat XMM registers as v4f32 as SSE1 targets don't permit other vector types.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvector-shuffle-sse1.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=SSE1
5 ; SSE1-LABEL: shuffle_v4f32_0001:
6 ; SSE1: # %bb.0:
7 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
8 ; SSE1-NEXT: retq
14 ; SSE1-LABEL: shuffle_v4f32_0020:
15 ; SSE1: # %bb.0:
16 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
17 ; SSE1-NEXT: retq
23 ; SSE1-LABEL: shuffle_v4f32_0300:
[all …]
Dunfold-masked-merge-vector-variablemask.ll3 …unknown-linux-gnu -mattr=+sse,-sse2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE,CHECK-SSE1
51 ; CHECK-SSE1-LABEL: out_v2i8:
52 ; CHECK-SSE1: # %bb.0:
53 ; CHECK-SSE1-NEXT: andl %r8d, %edi
54 ; CHECK-SSE1-NEXT: andl %r9d, %esi
55 ; CHECK-SSE1-NEXT: notb %r8b
56 ; CHECK-SSE1-NEXT: notb %r9b
57 ; CHECK-SSE1-NEXT: andb %cl, %r9b
58 ; CHECK-SSE1-NEXT: andb %dl, %r8b
59 ; CHECK-SSE1-NEXT: orb %dil, %r8b
[all …]
Dmerge-consecutive-loads-128.ll9 …iple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1
23 ; X32-SSE1-LABEL: merge_2f64_f64_23:
24 ; X32-SSE1: # %bb.0:
25 ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
26 ; X32-SSE1-NEXT: fldl 16(%eax)
27 ; X32-SSE1-NEXT: fldl 24(%eax)
28 ; X32-SSE1-NEXT: fxch %st(1)
29 ; X32-SSE1-NEXT: retl
56 ; X32-SSE1-LABEL: merge_2i64_i64_12:
57 ; X32-SSE1: # %bb.0:
[all …]
Dunfold-masked-merge-vector-variablemask-const.ll2 …unknown-linux-gnu -mattr=+sse,-sse2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE,CHECK-SSE1
11 ; CHECK-SSE1-LABEL: out_constant_varx_mone:
12 ; CHECK-SSE1: # %bb.0:
13 ; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
14 ; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [nan,nan,nan,nan]
15 ; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
16 ; CHECK-SSE1-NEXT: andps (%rsi), %xmm0
17 ; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
18 ; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
19 ; CHECK-SSE1-NEXT: movq %rdi, %rax
[all …]
Dvec_fneg.ll2 …ple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1
4 …e=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE1
55 ; X32-SSE1-LABEL: fneg_bitcast:
56 ; X32-SSE1: # %bb.0:
57 ; X32-SSE1-NEXT: pushl %ebp
58 ; X32-SSE1-NEXT: movl %esp, %ebp
59 ; X32-SSE1-NEXT: andl $-16, %esp
60 ; X32-SSE1-NEXT: subl $32, %esp
61 ; X32-SSE1-NEXT: movl $-2147483648, %eax # imm = 0x80000000
62 ; X32-SSE1-NEXT: movl 12(%ebp), %ecx
[all …]
Dmemcpy-2.ll3 …llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1
28 ; SSE1-LABEL: t1:
29 ; SSE1: movaps _.str, %xmm0
30 ; SSE1: movaps %xmm0
31 ; SSE1: movb $0, 24(%esp)
32 ; SSE1: movl $0, 20(%esp)
33 ; SSE1: movl $0, 16(%esp)
68 ; SSE1-LABEL: t2:
69 ; SSE1: movaps (%ecx), %xmm0
70 ; SSE1: movaps %xmm0, (%eax)
[all …]
Dmemset-sse-stack-realignment.ll5 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium3 | FileCheck %s -check-prefix=SSE1
21 ; SSE1-LABEL: test1:
22 ; SSE1: andl $-16
23 ; SSE1: movl %esp, %esi
24 ; SSE1: movaps
54 ; SSE1-LABEL: test2:
55 ; SSE1: andl $-16
56 ; SSE1: movl %esp, %esi
57 ; SSE1: movaps
Dmemcmp.ll3 …-unknown -mattr=+sse | FileCheck %s --check-prefix=X86 --check-prefix=SSE --check-prefix=X86-SSE1
571 ; X86-SSE1-LABEL: length16_eq:
572 ; X86-SSE1: # %bb.0:
573 ; X86-SSE1-NEXT: pushl $0
574 ; X86-SSE1-NEXT: pushl $16
575 ; X86-SSE1-NEXT: pushl {{[0-9]+}}(%esp)
576 ; X86-SSE1-NEXT: pushl {{[0-9]+}}(%esp)
577 ; X86-SSE1-NEXT: calll memcmp
578 ; X86-SSE1-NEXT: addl $16, %esp
579 ; X86-SSE1-NEXT: testl %eax, %eax
[all …]
Dsoft-fp.ll6 ; RUN: | FileCheck %s --check-prefix=SSE1 --check-prefix=CHECK
41 ; SSE1: xmm{{[0-9]+}}
54 ; SSE1: xmm{{[0-9]+}}
Dsse1.ll5 ; Tests for SSE1 and below, without SSE2+.
39 ; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
128 ; v4i32 isn't legal for SSE1, but this should be cmpps.
234 ; We now no longer try to lower sqrt using rsqrt with SSE1 only as the
Dinline-sse.ll6 ; PR16133 - we must treat XMM registers as v4f32 as SSE1 targets don't permit other vector types.
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dmemcpy-2.ll2 …llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1
18 ; SSE1: t1:
19 ; SSE1: movaps _.str, %xmm0
20 ; SSE1: movaps %xmm0
21 ; SSE1: movb $0
22 ; SSE1: movl $0
23 ; SSE1: movl $0
54 ; SSE1: t2:
55 ; SSE1: movaps (%eax), %xmm0
56 ; SSE1: movaps %xmm0, (%eax)
[all …]
Dsse1.ll1 ; Tests for SSE1 and below, without SSE2+.
/external/skqp/src/core/
DSkCpu.h15 SSE1 = 1 << 0, enumerator
63 features |= SSE1; in Supports()
92 features &= (SkCpu::SSE1 | SkCpu::SSE2 | SkCpu::SSE3 | SkCpu::SSSE3 | SkCpu::SSE41); in Supports()
94 features &= (SkCpu::SSE1 | SkCpu::SSE2); in Supports()
/external/skia/src/core/
DSkCpu.h15 SSE1 = 1 << 0, enumerator
63 features |= SSE1; in Supports()
92 features &= (SkCpu::SSE1 | SkCpu::SSE2 | SkCpu::SSE3 | SkCpu::SSSE3 | SkCpu::SSE41); in Supports()
94 features &= (SkCpu::SSE1 | SkCpu::SSE2); in Supports()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86Subtarget.h45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42 enumerator
173 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1()
DX86InstrFormats.td301 // SSE1 Instruction Templates:
303 // SSI - SSE1 instructions with XS prefix.
304 // PSI - SSE1 instructions with TB prefix.
305 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
306 // VSSI - SSE1 instructions with XS prefix in AVX form.
307 // VPSI - SSE1 instructions with TB prefix in AVX form.
/external/llvm/lib/Target/X86/
DX86Subtarget.h49 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
382 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1()

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