Home
last modified time | relevance | path

Searched refs:SUB2 (Results 1 – 25 of 25) sorted by relevance

/external/llvm/lib/Fuzzer/test/
Dfuzzer-dirs.test2 RUN: mkdir -p %t/SUB1/SUB2/SUB3
4 RUN: echo b > %t/SUB1/SUB2/b
5 RUN: echo c > %t/SUB1/SUB2/SUB3/c
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IRCE/
Dranges_of_different_types.ll29 ; CHECK-NEXT: [[SUB2:%[^ ]+]] = sub i32 -1, [[SMAX]]
30 ; CHECK-NEXT: [[CMP2:%[^ ]+]] = icmp sgt i32 [[SUB2]], 0
31 ; CHECK-NEXT: %exit.mainloop.at = select i1 [[CMP2]], i32 [[SUB2]], i32 0
90 ; CHECK-NEXT: [[SUB2:%[^ ]+]] = sub i32 -1, [[SMAX2]]
91 ; CHECK-NEXT: [[CMP3:%[^ ]+]] = icmp sgt i32 [[SUB2]], 0
92 ; CHECK-NEXT: %exit.mainloop.at = select i1 [[CMP3]], i32 [[SUB2]], i32 0
155 ; CHECK-NEXT: [[SUB2:%[^ ]+]] = sub i32 -1, %len
156 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp sgt i32 [[SUB2]], -14
157 ; CHECK-NEXT: [[SMAX1:%[^ ]+]] = select i1 [[CMP1]], i32 [[SUB2]], i32 -14
258 ; CHECK-NEXT: [[SUB2:%[^ ]+]] = sub i32 -1, [[SMAX]]
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Dfwd_dct32x32_msa.c95 SUB2(vec4, vec5, vec7, vec6, vec4, vec7); in fdct8x32_1d_column_even_store()
111 SUB2(in0, in1, in2, in3, in0, in2); in fdct8x32_1d_column_even_store()
117 SUB2(in9, vec2, in14, vec5, vec2, vec5); in fdct8x32_1d_column_even_store()
192 SUB2(in27, in26, in25, in24, in22, in21); in fdct8x32_1d_column_odd_store()
200 SUB2(in26, in27, in24, in25, in23, in20); in fdct8x32_1d_column_odd_store()
226 SUB2(in28, in29, in31, in30, in17, in18); in fdct8x32_1d_column_odd_store()
233 SUB2(in29, in28, in30, in31, in16, in19); in fdct8x32_1d_column_odd_store()
353 SUB2(vec4, vec5, vec7, vec6, vec4, vec7); in fdct8x32_1d_row_even_4x()
370 SUB2(in0, in1, in2, in3, in0, in2); in fdct8x32_1d_row_even_4x()
376 SUB2(in9, vec2, in14, vec5, vec2, vec5); in fdct8x32_1d_row_even_4x()
[all …]
Didct32x32_msa.c159 SUB2(reg5, reg4, reg3, reg2, vec0, vec1); in idct32x8_row_odd_process_store()
217 SUB2(reg0, reg4, reg1, reg5, vec0, vec1); in idct32x8_row_odd_process_store()
220 SUB2(reg2, reg6, reg3, reg7, vec0, vec1); in idct32x8_row_odd_process_store()
231 SUB2(reg0, reg4, reg3, reg7, vec0, vec1); in idct32x8_row_odd_process_store()
234 SUB2(reg1, reg5, reg2, reg6, vec0, vec1); in idct32x8_row_odd_process_store()
464 SUB2(reg5, reg4, reg3, reg2, vec0, vec1); in idct8x32_column_odd_process_store()
516 SUB2(reg0, reg4, reg1, reg5, vec0, vec1); in idct8x32_column_odd_process_store()
519 SUB2(reg2, reg6, reg3, reg7, vec0, vec1); in idct8x32_column_odd_process_store()
530 SUB2(reg0, reg4, reg3, reg7, vec0, vec1); in idct8x32_column_odd_process_store()
533 SUB2(reg1, reg5, reg2, reg6, vec0, vec1); in idct8x32_column_odd_process_store()
Dfwd_txfm_msa.c134 SUB2(stp34, stp25, stp33, stp22, in12, in11); in fdct8x16_1d_column()
Dinv_txfm_msa.h228 SUB2(in1, in3, in7, in5, res0_m, res1_m); \
Dmacros_msa.h1571 #define SUB2(in0, in1, in2, in3, out0, out1) \ macro
/external/libaom/libaom/av1/encoder/mips/msa/
Dfdct4x4_msa.c25 SUB2(in4, in1, in4, in2, in1, in2); in av1_fwht4x4_msa()
34 SUB2(in4, in2, in4, in3, in2, in3); in av1_fwht4x4_msa()
/external/libvpx/libvpx/vp8/encoder/mips/msa/
Dquantize_msa.c58 SUB2(x0, sign_z0, x1, sign_z1, x0, x1); in fast_quantize_b_msa()
121 SUB2(x0, z_bin0, x1, z_bin1, z_bin0, z_bin1); in exact_regular_quantize_b_msa()
122 SUB2(z_bin0, zbin_o_q, z_bin1, zbin_o_q, z_bin0, z_bin1); in exact_regular_quantize_b_msa()
145 SUB2(sign_x0, sign_z0, sign_x1, sign_z1, sign_x0, sign_x1); in exact_regular_quantize_b_msa()
Ddenoising_msa.c214 SUB2(zero, abs_diff0, zero, abs_diff1, abs_diff_neg0, abs_diff_neg1); in vp8_denoiser_filter_msa()
250 SUB2(zero, abs_diff0, zero, abs_diff1, abs_diff_neg0, abs_diff_neg1); in vp8_denoiser_filter_msa()
/external/libvpx/libvpx/vp9/encoder/mips/msa/
Dvp9_fdct4x4_msa.c25 SUB2(in4, in1, in4, in2, in1, in2); in vp9_fwht4x4_msa()
34 SUB2(in4, in2, in4, in3, in2, in3); in vp9_fwht4x4_msa()
/external/webp/src/dsp/
Dlossless_enc_msa.c33 SUB2(t0, t2, t1, t3, t0, t1); \
109 SUB2(src0, tmp0, src1, tmp1, dst0, dst1); in SubtractGreenFromBlueAndRed_MSA()
Dfilters_msa.c31 SUB2(src0, pred0, src1, pred1, dst0, dst1); in PredictLineInverse0()
115 SUB2(a0, c0, a1, c1, a0, a1); in PredictLineGradient()
Drescaler_msa.c318 SUB2(src0, frac0, src1, frac1, src0, src1);
Denc_msa.c493 SUB2(d1, TL, d2, TL, d1, d2); in TrueMotion16x16()
835 SUB2(zero, tmp2, zero, tmp3, tmp0, tmp1); in QuantizeBlock_MSA()
Dupsampling_msa.c557 SUB2(t0, t2, t1, t3, diag1, diag2); \
Dmsa_macro.h1186 #define SUB2(in0, in1, in2, in3, out0, out1) do { \ macro
Ddec_msa.c802 SUB2(d1, TL, d2, TL, d1, d2); in TM16()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LICM/
Dsinking.ll465 ; CHECK: %[[SUB2:.*]] = sub i32 %[[MUL2]], %N
469 ; CHECK: phi i32 [ %[[SUB]], %Out12.split.loop.exit ], [ %[[SUB2]], %Out12.split.loop.exit1 ]
/external/llvm/test/Transforms/InstCombine/
Dicmp.ll1537 ; CHECK-NEXT: [[SUB2:%.*]] = sub i32 %Y, %X
1540 ; CHECK-NEXT: [[RES_IN_IN:%.*]] = phi i32 [ [[ADD]], %true ], [ [[SUB2]], %false ]
1572 ; CHECK-NEXT: [[SUB2:%.*]] = sub i32 %Y, %X
1575 ; CHECK-NEXT: [[RES_IN_IN:%.*]] = phi i32 [ [[SUB]], %true ], [ [[SUB2]], %false ]
/external/pcre/dist2/src/
Dpcre2test.c1480 #define SUB2(a,b,c) \ macro
1934 #define SUB2(a,b,c) \ macro
2053 #define SUB2(a,b,c) G(a,8)(G(b,8),G(c,8)) macro
2157 #define SUB2(a,b,c) G(a,16)(G(b,16),G(c,16)) macro
2261 #define SUB2(a,b,c) G(a,32)(G(b,32),G(c,32)) macro
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dicmp.ll2186 ; CHECK-NEXT: [[SUB2:%.*]] = sub i32 %Y, %X
2189 ; CHECK-NEXT: [[RES_IN_IN:%.*]] = phi i32 [ [[ADD]], %true ], [ [[SUB2]], %false ]
2221 ; CHECK-NEXT: [[SUB2:%.*]] = sub i32 %Y, %X
2224 ; CHECK-NEXT: [[RES_IN_IN:%.*]] = phi i32 [ [[SUB]], %true ], [ [[SUB2]], %false ]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCInstrInfo.td226 defm SUB2 : ArcBinaryGEN4Inst<0b011000, "sub2">;
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h1468 #define SUB2(in0, in1, in2, in3, out0, out1) \ macro
/external/libaom/libaom/aom_dsp/mips/
Dmacros_msa.h1675 #define SUB2(in0, in1, in2, in3, out0, out1) \ macro