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Searched refs:SUNXI_SRAMC_BASE (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/
Dboard.c161 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); in s_init()
166 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); in s_init()
167 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; in s_init()
168 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); in s_init()
177 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); in s_init()
179 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); in s_init()
182 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); in s_init()
Dcpu_info.c46 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); in sunxi_get_sram_id()
47 id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; in sunxi_get_sram_id()
48 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); in sunxi_get_sram_id()
Ddram_sunxi_dw.c279 if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 && in mctl_h3_zq_calibration_quirk()
280 (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) { in mctl_h3_zq_calibration_quirk()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Dcpu_sun4i.h26 #define SUNXI_SRAMC_BASE 0x01c00000 macro
/external/u-boot/drivers/video/sunxi/
Dsunxi_de2.c42 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
44 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
/external/u-boot/drivers/usb/musb-new/
Dsunxi.c174 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
177 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
/external/u-boot/arch/arm/cpu/armv7/sunxi/
Dpsci.c125 SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); in sunxi_set_entry_address()
/external/u-boot/drivers/net/
Dsunxi_emac.c508 (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; in sunxi_emac_board_setup()