| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 3245 PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, in isSignOrZeroExtended() argument
3252 if (SignExt ? isSignExtendingOp(MI): in isSignOrZeroExtended()
3269 return SignExt ? FuncInfo->isLiveInSExt(VReg) : in isSignOrZeroExtended()
3296 return Attrs.hasAttribute(SignExt ? Attribute::SExt : in isSignOrZeroExtended()
3308 return isSignOrZeroExtended(*SrcMI, SignExt, Depth); in isSignOrZeroExtended()
3332 return isSignOrZeroExtended(*SrcMI, SignExt, Depth); in isSignOrZeroExtended()
3360 if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1)) in isSignOrZeroExtended()
3391 if(SignExt) in isSignOrZeroExtended()
3392 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) && in isSignOrZeroExtended()
3393 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1); in isSignOrZeroExtended()
[all …]
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| D | PPCInstrInfo.h | 354 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2496 static bool SearchSignedMulShort(SDValue SignExt, unsigned *Opc, SDValue &Src1, in SearchSignedMulShort() argument
2501 if ((SignExt.getOpcode() == ISD::SIGN_EXTEND || in SearchSignedMulShort()
2502 SignExt.getOpcode() == ISD::SIGN_EXTEND_INREG || in SearchSignedMulShort()
2503 SignExt.getOpcode() == ISD::AssertSext) && in SearchSignedMulShort()
2504 SignExt.getValueType() == MVT::i32) { in SearchSignedMulShort()
2507 Src1 = SignExt.getOperand(0); in SearchSignedMulShort()
2511 if (SignExt.getOpcode() != ISD::SRA) in SearchSignedMulShort()
2514 ConstantSDNode *SRASrc1 = dyn_cast<ConstantSDNode>(SignExt.getOperand(1)); in SearchSignedMulShort()
2518 SDValue Op0 = SignExt.getOperand(0); in SearchSignedMulShort()
2532 Src1 = SignExt.getOperand(0); in SearchSignedMulShort()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 1034 auto GuessNonIVOperand = [&](bool SignExt) { in cloneArithmeticIVUser() argument
1038 auto GetExtend = [this, SignExt](const SCEV *S, Type *Ty) { in cloneArithmeticIVUser()
1039 if (SignExt) in cloneArithmeticIVUser()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstMIPS32.cpp | 39 bool OperandMIPS32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) { in canHoldOffset() argument
40 (void)SignExt; in canHoldOffset()
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| D | IceTargetLoweringMIPS32.cpp | 1822 constexpr bool SignExt = true; in newBaseRegister() local
1823 if (!OperandMIPS32Mem::canHoldOffset(Base->getType(), SignExt, Offset)) { in newBaseRegister()
2138 constexpr bool SignExt = true; in legalizeMemOperand() local
2139 if (!OperandMIPS32Mem::canHoldOffset(Mem->getType(), SignExt, Offset)) { in legalizeMemOperand()
2318 constexpr bool SignExt = false; in hiOperand() local
2319 if (!OperandMIPS32Mem::canHoldOffset(SplitType, SignExt, NextOffsetVal)) { in hiOperand()
3466 constexpr bool SignExt = false; in lowerCall() local
3467 if (OperandMIPS32Mem::canHoldOffset(Ty, SignExt, StackArg.second)) { in lowerCall()
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| D | IceInstARM32.cpp | 352 bool OperandARM32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) { in canHoldOffset() argument
353 int32_t Bits = SignExt ? TypeARM32Attributes[Ty].SExtAddrOffsetBits in canHoldOffset()
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| D | IceInstMIPS32.h | 150 static bool canHoldOffset(Type Ty, bool SignExt, int32_t Offset);
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| D | IceInstARM32.h | 149 static bool canHoldOffset(Type Ty, bool SignExt, int32_t Offset);
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| D | IceTargetLoweringARM32.cpp | 3764 constexpr bool SignExt = false; in lowerCall() local
3765 if (OperandARM32Mem::canHoldOffset(Ty, SignExt, StackArg.second)) { in lowerCall()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 1132 auto GuessNonIVOperand = [&](bool SignExt) { in cloneArithmeticIVUser() argument
1136 auto GetExtend = [this, SignExt](const SCEV *S, Type *Ty) { in cloneArithmeticIVUser()
1137 if (SignExt) in cloneArithmeticIVUser()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 19297 SDValue SignExt = Curr; in LowerEXTEND_VECTOR_INREG() local
19301 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr, in LowerEXTEND_VECTOR_INREG()
19306 return SignExt; in LowerEXTEND_VECTOR_INREG()
19311 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5}); in LowerEXTEND_VECTOR_INREG()
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