Searched refs:SimFloat16 (Results 1 – 6 of 6) sorted by relevance
| /external/vixl/src/ |
| D | utils-vixl.cc | 95 uint32_t Float16Sign(internal::SimFloat16 val) { in Float16Sign()
101 uint32_t Float16Exp(internal::SimFloat16 val) { in Float16Exp()
106 uint32_t Float16Mantissa(internal::SimFloat16 val) { in Float16Mantissa()
148 internal::SimFloat16 Float16Pack(uint16_t sign, in Float16Pack()
215 SimFloat16 SimFloat16::operator-() const { in operator -()
220 SimFloat16 SimFloat16::operator+(SimFloat16 rhs) const { in operator +()
224 SimFloat16 SimFloat16::operator-(SimFloat16 rhs) const { in operator -()
228 SimFloat16 SimFloat16::operator*(SimFloat16 rhs) const { in operator *()
232 SimFloat16 SimFloat16::operator/(SimFloat16 rhs) const { in operator /()
236 bool SimFloat16::operator<(SimFloat16 rhs) const { in operator <()
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| D | utils-vixl.h | 278 class SimFloat16 : public Float16 {
283 SimFloat16(double dvalue) : Float16(dvalue) {} // NOLINT(runtime/explicit) in SimFloat16() function
284 SimFloat16(Float16 f) { // NOLINT(runtime/explicit) in SimFloat16() function
287 SimFloat16() : Float16() {} in SimFloat16() function
288 SimFloat16 operator-() const;
289 SimFloat16 operator+(SimFloat16 rhs) const;
290 SimFloat16 operator-(SimFloat16 rhs) const;
291 SimFloat16 operator*(SimFloat16 rhs) const;
292 SimFloat16 operator/(SimFloat16 rhs) const;
293 bool operator<(SimFloat16 rhs) const;
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| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 46 ::vixl::internal::SimFloat16 f1 = kFP16DefaultNaN; in TEST()
47 ::vixl::internal::SimFloat16 f2 = kFP16DefaultNaN; in TEST()
48 ::vixl::internal::SimFloat16 f3 = kFP16PositiveInfinity; in TEST()
49 ::vixl::internal::SimFloat16 f4 = kFP16NegativeInfinity; in TEST()
54 VIXL_CHECK(::vixl::internal::SimFloat16(kFP16PositiveZero) == in TEST()
55 ::vixl::internal::SimFloat16(kFP16NegativeZero)); in TEST()
56 VIXL_CHECK(!(::vixl::internal::SimFloat16(kFP16PositiveZero) != in TEST()
57 ::vixl::internal::SimFloat16(kFP16NegativeZero))); in TEST()
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| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 36 using vixl::internal::SimFloat16;
65 bool IsFloat16<SimFloat16>() { in IsFloat16()
82 SimFloat16 Simulator::FPDefaultNaN<SimFloat16>() { in FPDefaultNaN()
83 return SimFloat16(kFP16DefaultNaN); in FPDefaultNaN()
141 SimFloat16 Simulator::FixedToFloat16(int64_t src, int fbits, FPRounding round) { in FixedToFloat16()
152 SimFloat16 Simulator::UFixedToFloat16(uint64_t src, in UFixedToFloat16()
3906 bool IsNormal(SimFloat16 value) { in IsNormal()
4174 FN<SimFloat16>(vform, dst, src1, src2); \
4218 frecps<SimFloat16>(vform, dst, src1, src2); in frecps()
4250 frsqrts<SimFloat16>(vform, dst, src1, src2); in frsqrts()
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| D | simulator-aarch64.h | 179 inline void SimVRegister::ReadLane(vixl::internal::SimFloat16* dst, in ReadLane()
188 inline void SimVRegister::WriteLane(vixl::internal::SimFloat16 src, int lane) { in WriteLane()
1007 vixl::internal::SimFloat16 ReadHRegister(unsigned code) const {
1128 vixl::internal::SimFloat16 value,
3021 ::vixl::internal::SimFloat16 FixedToFloat16(int64_t src,
3024 ::vixl::internal::SimFloat16 UFixedToFloat16(uint64_t src,
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| D | simulator-aarch64.cc | 38 using vixl::internal::SimFloat16;
3197 FPCompare(ReadHRegister(instr->GetRn()), SimFloat16(0.0), trap); in VisitFPCompare()
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