Searched refs:SubIndices (Results 1 – 9 of 9) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 251 SmallVectorImpl<unsigned> &SubIndices, in canCombineSubRegIndices() argument
259 unsigned NumRegs = SubIndices.size(); in canCombineSubRegIndices()
263 SubIndices[0] == ARM::dsub_0 && in canCombineSubRegIndices()
264 SubIndices[1] == ARM::dsub_1 && in canCombineSubRegIndices()
265 SubIndices[2] == ARM::dsub_2 && in canCombineSubRegIndices()
266 SubIndices[3] == ARM::dsub_3 && in canCombineSubRegIndices()
267 SubIndices[4] == ARM::dsub_4 && in canCombineSubRegIndices()
268 SubIndices[5] == ARM::dsub_5 && in canCombineSubRegIndices()
269 SubIndices[6] == ARM::dsub_6 && in canCombineSubRegIndices()
270 SubIndices[7] == ARM::dsub_7); in canCombineSubRegIndices()
[all …]
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| D | ARMBaseRegisterInfo.h | 115 SmallVectorImpl<unsigned> &SubIndices,
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| /external/capstone/ |
| D | MCRegisterInfo.c | 35 uint16_t *SubIndices, unsigned NumIndices, in MCRegisterInfo_InitMCRegisterInfo() argument
48 RI->SubRegIndices = SubIndices; in MCRegisterInfo_InitMCRegisterInfo()
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| D | MCRegisterInfo.h | 103 uint16_t *SubIndices,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 392 ArrayRef<int16_t> SubIndices; in copyPhysReg() local
425 SubIndices = Sub0_3_64; in copyPhysReg()
430 SubIndices = Sub0_7_64; in copyPhysReg()
435 SubIndices = Sub0_15_64; in copyPhysReg()
448 SubIndices = Sub0_1; in copyPhysReg()
453 SubIndices = Sub0_2; in copyPhysReg()
459 SubIndices = Sub0_3; in copyPhysReg()
465 SubIndices = Sub0_7; in copyPhysReg()
471 SubIndices = Sub0_15; in copyPhysReg()
482 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) { in copyPhysReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 254 const uint16_t *SubIndices, in InitMCRegisterInfo() argument
270 SubRegIndices = SubIndices; in InitMCRegisterInfo()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 254 const uint16_t *SubIndices, in InitMCRegisterInfo() argument
270 SubRegIndices = SubIndices; in InitMCRegisterInfo()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 397 SmallVectorImpl<unsigned> &SubIndices, in canCombineSubRegIndices() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 577 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize); in copyPhysReg() local
580 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) { in copyPhysReg()
583 SubIdx = SubIndices[Idx]; in copyPhysReg()
585 SubIdx = SubIndices[SubIndices.size() - Idx - 1]; in copyPhysReg()
595 bool UseKill = KillSrc && Idx == SubIndices.size() - 1; in copyPhysReg()
664 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize); in materializeImmediate() local
665 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) { in materializeImmediate()
1878 const int16_t *SubIndices = Sub0_15; in insertSelect() local
1885 SubIndices = Sub0_15_64; in insertSelect()
1901 unsigned SubIdx = SubIndices[Idx]; in insertSelect()
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