| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 570 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
573 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
574 SuperReg = Reg; in FindSuitableFreeRegisters()
593 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
594 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
607 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << in FindSuitableFreeRegisters()
621 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
644 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
655 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
658 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| D | CriticalAntiDepBreaker.cpp | 284 unsigned SuperReg = *Super; in ScanInstruction() local
285 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1); in ScanInstruction()
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| D | PostRASchedulerList.cpp | 416 const unsigned SuperReg = MO.getReg(); in ToggleKillFlag() local
417 for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg); in ToggleKillFlag()
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| D | LiveIntervalAnalysis.cpp | 2069 unsigned SuperReg = *AS; in getRepresentativeReg() local
2070 if (!hasAllocatableSuperReg(SuperReg) && hasInterval(SuperReg)) { in getRepresentativeReg()
2071 BestReg = SuperReg; in getRepresentativeReg()
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| D | VirtRegRewriter.cpp | 2562 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI); in RewriteMBB() local
2563 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg && in RewriteMBB()
2565 PhysReg = SuperReg; in RewriteMBB()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 575 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
578 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
579 SuperReg = Reg; in FindSuitableFreeRegisters()
601 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
602 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
617 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) in FindSuitableFreeRegisters()
631 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
653 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
664 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
667 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 556 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
559 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
560 SuperReg = Reg; in FindSuitableFreeRegisters()
582 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
583 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
598 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << in FindSuitableFreeRegisters()
612 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
634 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
645 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
648 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| D | ScheduleDAGInstrs.cpp | 1258 const unsigned SuperReg = MO.getReg(); in toggleKillFlag() local
1260 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) { in toggleKillFlag()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 658 unsigned SuperReg = MI->getOperand(0).getReg(); in spillSGPR() local
668 assert(SpillToVGPR || (SuperReg != MFI->getStackPtrOffsetReg() && in spillSGPR()
669 SuperReg != MFI->getFrameOffsetReg() && in spillSGPR()
670 SuperReg != MFI->getScratchWaveOffsetReg())); in spillSGPR()
672 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in spillSGPR()
687 const TargetRegisterClass *RC = getPhysRegClass(SuperReg); in spillSGPR()
702 SuperReg : getSubReg(SuperReg, SplitParts[i]); in spillSGPR()
788 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState); in spillSGPR()
837 unsigned SuperReg = MI->getOperand(0).getReg(); in restoreSGPR() local
842 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in restoreSGPR()
[all …]
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| D | SIInstrInfo.h | 69 MachineOperand &SuperReg,
75 MachineOperand &SuperReg,
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| D | SIInstrInfo.cpp | 3101 MachineOperand &SuperReg, in buildExtractSubReg() argument
3110 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { in buildExtractSubReg()
3112 .addReg(SuperReg.getReg(), 0, SubIdx); in buildExtractSubReg()
3123 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 849 unsigned SuperReg = in copyPhysReg() local
852 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
855 DestReg = SuperReg; in copyPhysReg()
858 unsigned SuperReg = in copyPhysReg() local
861 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
864 DestReg = SuperReg; in copyPhysReg()
867 unsigned SuperReg = in copyPhysReg() local
870 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
873 SrcReg = SuperReg; in copyPhysReg()
876 unsigned SuperReg = in copyPhysReg() local
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 46 MachineOperand &SuperReg,
52 MachineOperand &SuperReg,
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| D | SIRegisterInfo.cpp | 520 unsigned SuperReg = MI->getOperand(0).getReg(); in eliminateFrameIndex() local
525 unsigned SubReg = getPhysRegSubReg(SuperReg, in eliminateFrameIndex()
556 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState); in eliminateFrameIndex()
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| D | SIInstrInfo.cpp | 1903 MachineOperand &SuperReg, in buildExtractSubReg() argument
1912 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { in buildExtractSubReg()
1914 .addReg(SuperReg.getReg(), 0, SubIdx); in buildExtractSubReg()
1925 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
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| D | R600InstrInfo.cpp | 1120 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index); in reserveIndirectRegisters() local
1121 Reserved.set(SuperReg); in reserveIndirectRegisters()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1663 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
1669 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
1887 SDValue SuperReg; in SelectVLDSTLane() local
1892 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
1894 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
1901 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
1903 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
1905 Ops.push_back(SuperReg); in SelectVLDSTLane()
1920 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
1926 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1930 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
1937 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2166 SDValue SuperReg; in SelectVLDSTLane() local
2171 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2173 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2180 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2182 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2184 Ops.push_back(SuperReg); in SelectVLDSTLane()
2200 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2207 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1867 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
1874 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2111 SDValue SuperReg; in SelectVLDSTLane() local
2116 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2118 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2125 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2127 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2129 Ops.push_back(SuperReg); in SelectVLDSTLane()
2145 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2152 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1203 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1206 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1237 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1239 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1243 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1350 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
1356 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1399 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
1402 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
1409 SuperReg); in SelectPostLoadLane()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1146 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1149 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1174 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1176 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1180 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1282 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
1288 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1331 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
1334 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
1341 SuperReg); in SelectPostLoadLane()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 901 unsigned SuperReg = in copyPhysReg() local
904 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
907 DestReg = SuperReg; in copyPhysReg()
910 unsigned SuperReg = in copyPhysReg() local
913 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
916 SrcReg = SuperReg; in copyPhysReg()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6066 unsigned SuperReg = MRI->getMatchingSuperReg( in ParseInstruction() local
6069 assert(SuperReg && "expected register pair"); in ParseInstruction()
6071 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); in ParseInstruction()
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