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Searched refs:TMP2 (Results 1 – 25 of 349) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
D	bswap-fold.ll	`8 ; CHECK-NEXT: [[TMP2:%.]] = and i32 %a, 255 9 ; CHECK-NEXT: ret i32 [[TMP2]] 19 ; CHECK-NEXT: [[TMP2:%.]] = lshr i32 %a, 24 20 ; CHECK-NEXT: ret i32 [[TMP2]] 67 ; CHECK-NEXT: [[TMP2:%.]] = call i16 @llvm.bswap.i16(i16 [[TMP1]]) 68 ; CHECK-NEXT: ret i16 [[TMP2]] 78 ; CHECK-NEXT: [[TMP2:%.]] = call i16 @llvm.bswap.i16(i16 [[TMP1]]) 79 ; CHECK-NEXT: ret i16 [[TMP2]] 90 ; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP1]]) 91 ; CHECK-NEXT: ret i16 [[TMP2]] [all …]`
D	pow-4.ll	11 ; CHECK-NEXT: [[TMP2:%.]] = fmul fast float [[TMP1]], [[TMP1]] 12 ; CHECK-NEXT: ret float [[TMP2]] 22 ; CHECK-NEXT: [[TMP2:%.]] = fmul fast double [[TMP1]], [[X]] 23 ; CHECK-NEXT: ret double [[TMP2]] 33 ; CHECK-NEXT: [[TMP2:%.]] = fmul fast double [[TMP1]], [[TMP1]] 34 ; CHECK-NEXT: ret double [[TMP2]] 44 ; CHECK-NEXT: [[TMP2:%.]] = fmul fast double [[TMP1]], [[X]] 45 ; CHECK-NEXT: [[TMP3:%.]] = fmul fast double [[TMP2]], [[TMP2]] 47 ; CHECK-NEXT: [[TMP5:%.]] = fmul fast double [[TMP2]], [[TMP4]] 58 ; CHECK-NEXT: [[TMP2:%.*]] = fmul fast double [[TMP1]], [[TMP1]] [all …]
D	canonicalize-signed-truncation-check.ll	19 ; CHECK-NEXT: [[TMP2:%.]] = icmp ugt i8 [[TMP1]], 7 20 ; CHECK-NEXT: ret i1 [[TMP2]] 32 ; CHECK-NEXT: [[TMP2:%.]] = icmp slt i65 [[TMP1]], 0 33 ; CHECK-NEXT: ret i1 [[TMP2]] 48 ; CHECK-NEXT: [[TMP2:%.]] = icmp ugt <2 x i8> [[TMP1]], <i8 7, i8 7> 49 ; CHECK-NEXT: ret <2 x i1> [[TMP2]] 61 ; CHECK-NEXT: [[TMP2:%.]] = icmp ne <2 x i8> [[TMP1]], [[X]] 62 ; CHECK-NEXT: ret <2 x i1> [[TMP2]] 74 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <3 x i8> [[TMP1]], [[X]] 75 ; CHECK-NEXT: ret <3 x i1> [[TMP2]] [all …]
D	canonicalize-lack-of-signed-truncation-check.ll	19 ; CHECK-NEXT: [[TMP2:%.]] = icmp ult i8 [[TMP1]], 8 20 ; CHECK-NEXT: ret i1 [[TMP2]] 32 ; CHECK-NEXT: [[TMP2:%.]] = icmp sgt i65 [[TMP1]], -1 33 ; CHECK-NEXT: ret i1 [[TMP2]] 48 ; CHECK-NEXT: [[TMP2:%.]] = icmp ult <2 x i8> [[TMP1]], <i8 8, i8 8> 49 ; CHECK-NEXT: ret <2 x i1> [[TMP2]] 61 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq <2 x i8> [[TMP1]], [[X]] 62 ; CHECK-NEXT: ret <2 x i1> [[TMP2]] 74 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <3 x i8> [[TMP1]], [[X]] 75 ; CHECK-NEXT: ret <3 x i1> [[TMP2]] [all …]
D	and-narrow.ll	10 ; CHECK-NEXT: [[TMP2:%.]] = and i8 [[TMP1]], [[X]] 11 ; CHECK-NEXT: [[R:%.]] = zext i8 [[TMP2]] to i16 23 ; CHECK-NEXT: [[TMP2:%.]] = and i8 [[TMP1]], [[X]] 24 ; CHECK-NEXT: [[R:%.]] = zext i8 [[TMP2]] to i16 36 ; CHECK-NEXT: [[TMP2:%.]] = and i8 [[TMP1]], [[X]] 37 ; CHECK-NEXT: [[R:%.]] = zext i8 [[TMP2]] to i16 49 ; CHECK-NEXT: [[TMP2:%.]] = and i8 [[TMP1]], [[X]] 50 ; CHECK-NEXT: [[R:%.]] = zext i8 [[TMP2]] to i16 62 ; CHECK-NEXT: [[TMP2:%.]] = and i8 [[TMP1]], [[X]] 63 ; CHECK-NEXT: [[R:%.]] = zext i8 [[TMP2]] to i16 [all …]
D	select-of-bittest.ll	11 ; CHECK-NEXT: [[TMP2:%.]] = icmp ne i32 [[TMP1]], 0 12 ; CHECK-NEXT: [[TMP4:%.]] = zext i1 [[TMP2]] to i32 26 ; CHECK-NEXT: [[TMP2:%.]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer 27 ; CHECK-NEXT: [[TMP4:%.]] = zext <2 x i1> [[TMP2]] to <2 x i32> 41 ; CHECK-NEXT: [[TMP2:%.]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer 42 ; CHECK-NEXT: [[TMP4:%.]] = zext <2 x i1> [[TMP2]] to <2 x i32> 56 ; CHECK-NEXT: [[TMP2:%.]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer 57 ; CHECK-NEXT: [[TMP4:%.]] = zext <2 x i1> [[TMP2]] to <2 x i32> 71 ; CHECK-NEXT: [[TMP2:%.]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer 72 ; CHECK-NEXT: [[TMP4:%.]] = zext <2 x i1> [[TMP2]] to <2 x i32> [all …]
D	minmax-fp.ll	9 ; CHECK-NEXT: [[TMP2:%.]] = fpext float [[TMP1]] to double 10 ; CHECK-NEXT: ret double [[TMP2]] 23 ; CHECK-NEXT: [[TMP2:%.]] = fpext float [[TMP1]] to double 24 ; CHECK-NEXT: ret double [[TMP2]] 37 ; CHECK-NEXT: [[TMP2:%.]] = fptrunc double [[TMP1]] to float 38 ; CHECK-NEXT: ret float [[TMP2]] 50 ; CHECK-NEXT: [[TMP2:%.]] = fpext float %a to double 51 ; CHECK-NEXT: [[TMP3:%.]] = select i1 [[TMP1]], double [[TMP2]], double 5.001000e+00 64 ; CHECK-NEXT: [[TMP2:%.]] = fpext float %a to double 65 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], double [[TMP2]], double 0.000000e+00 [all …]
D	sign-test-and-or.ll	`9 ; CHECK-NEXT: [[TMP2:%.]] = icmp slt i32 [[TMP1]], 0 10 ; CHECK-NEXT: ret i1 [[TMP2]] 21 ; CHECK-NEXT: [[TMP2:%.]] = icmp sgt i32 [[TMP1]], -1 22 ; CHECK-NEXT: ret i1 [[TMP2]] 33 ; CHECK-NEXT: [[TMP2:%.]] = icmp slt i32 [[TMP1]], 0 34 ; CHECK-NEXT: ret i1 [[TMP2]] 45 ; CHECK-NEXT: [[TMP2:%.]] = icmp sgt i32 [[TMP1]], -1 46 ; CHECK-NEXT: ret i1 [[TMP2]] 57 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 58 ; CHECK-NEXT: br i1 [[TMP2]], label %if.then, label %if.end [all …]`
D	and-or-icmps.ll	`29 ; CHECK-NEXT: [[TMP2:%.]] = icmp ult i32 [[TMP1]], 8 30 ; CHECK-NEXT: ret i1 [[TMP2]] 45 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq i32 [[TMP1]], 51 46 ; CHECK-NEXT: ret i1 [[TMP2]] 59 ; CHECK-NEXT: [[TMP2:%.]] = icmp ne i32 [[TMP1]], 51 60 ; CHECK-NEXT: ret i1 [[TMP2]] 73 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq i32 [[TMP1]], 97 74 ; CHECK-NEXT: ret i1 [[TMP2]] 85 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i19 [[TMP1]], 193 86 ; CHECK-NEXT: ret i1 [[TMP2]] [all …]`
D	unsigned_saturated_sub.ll	16 ; CHECK-NEXT: [[TMP2:%.]] = select i1 [[TMP1]], i64 [[A]], i64 [[B]] 17 ; CHECK-NEXT: [[TMP3:%.]] = sub i64 [[TMP2]], [[B]] 31 ; CHECK-NEXT: [[TMP2:%.]] = select i1 [[TMP1]], i64 [[B]], i64 [[A]] 32 ; CHECK-NEXT: [[TMP3:%.]] = sub i64 [[TMP2]], [[B]] 47 ; CHECK-NEXT: [[TMP2:%.]] = select <4 x i1> [[TMP1]], <4 x i32> [[A]], <4 x i32> [[B]] 48 ; CHECK-NEXT: [[TMP3:%.]] = sub <4 x i32> [[TMP2]], [[B]] 63 ; CHECK-NEXT: [[TMP2:%.]] = select i1 [[TMP1]], i64 [[A]], i64 [[B]] 64 ; CHECK-NEXT: [[TMP3:%.]] = sub i64 [[TMP2]], [[B]] 82 ; CHECK-NEXT: [[TMP2:%.]] = select i1 [[TMP1]], i64 [[B]], i64 [[A]] 83 ; CHECK-NEXT: [[TMP3:%.]] = sub i64 [[TMP2]], [[B]] [all …]
D	select-bitext-bitwise-ops.ll	7 ; CHECK-NEXT: [[TMP2:%.]] = shl nuw nsw i32 [[TMP1]], 2 9 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] 26 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], 60 27 ; CHECK-NEXT: [[TMP3:%.]] = zext i32 [[TMP2]] to i64 43 ; CHECK-NEXT: [[TMP2:%.]] = lshr exact i32 [[TMP1]], 2 45 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] 62 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], 15 63 ; CHECK-NEXT: [[TMP3:%.]] = zext i32 [[TMP2]] to i64 79 ; CHECK-NEXT: [[TMP2:%.]] = ashr exact i32 [[TMP1]], 2 81 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] [all …]
D	vector-udiv.ll	26 ; CHECK-NEXT: [[TMP2:%.]] = zext <4 x i1> [[TMP1]] to <4 x i32> 27 ; CHECK-NEXT: ret <4 x i32> [[TMP2]] 36 ; CHECK-NEXT: [[TMP2:%.]] = zext <4 x i1> [[TMP1]] to <4 x i32> 37 ; CHECK-NEXT: ret <4 x i32> [[TMP2]] 55 ; CHECK-NEXT: [[TMP2:%.]] = lshr <4 x i32> [[A0:%.]], [[TMP1]] 56 ; CHECK-NEXT: ret <4 x i32> [[TMP2]] 66 ; CHECK-NEXT: [[TMP2:%.]] = lshr <4 x i32> [[A0:%.]], [[TMP1]] 67 ; CHECK-NEXT: ret <4 x i32> [[TMP2]] 78 ; CHECK-NEXT: [[TMP2:%.]] = zext <4 x i16> [[TMP1]] to <4 x i32> 79 ; CHECK-NEXT: [[TMP3:%.]] = lshr <4 x i32> [[A0:%.*]], [[TMP2]] [all …]
D	select-icmp-and.ll	113 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq i64 [[TMP1]], 0 114 ; CHECK-NEXT: [[TMP3:%.]] = select i1 [[TMP2]], i32 42, i32 40 126 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq <2 x i64> [[TMP1]], zeroinitializer 127 ; CHECK-NEXT: [[TMP3:%.]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i3… 139 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq i64 [[TMP1]], 0 140 ; CHECK-NEXT: [[TMP3:%.]] = select i1 [[TMP2]], i32 42, i32 40 152 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq <2 x i64> [[TMP1]], zeroinitializer 153 ; CHECK-NEXT: [[TMP3:%.]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i3… 166 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq i64 [[TMP1]], 0 167 ; CHECK-NEXT: [[TMP3:%.]] = select i1 [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, … [all …]
D	or-shifted-masks.ll	6 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], 8 9 ; CHECK-NEXT: [[TMP5:%.]] = or i32 [[TMP2]], [[TMP4]] 23 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], 896 26 ; CHECK-NEXT: [[TMP5:%.]] = or i32 [[TMP2]], [[TMP4]] 40 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], 56 43 ; CHECK-NEXT: [[TMP5:%.]] = or i32 [[TMP2]], [[TMP4]] 57 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], 384 60 ; CHECK-NEXT: [[TMP5:%.]] = or i32 [[TMP4]], [[TMP2]] 78 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], 12 86 ; CHECK-NEXT: [[TMP10:%.]] = or i32 [[TMP2]], [[TMP9]] [all …]
D	fmul-sqrt.ll	12 ; CHECK-NEXT: [[TMP2:%.]] = call double @llvm.sqrt.f64(double [[B:%.]]) 13 ; CHECK-NEXT: [[MUL:%.]] = fmul double [[TMP1]], [[TMP2]] 27 ; CHECK-NEXT: [[TMP2:%.]] = call fast double @llvm.sqrt.f64(double [[B:%.]]) 28 ; CHECK-NEXT: [[MUL:%.]] = fmul fast double [[TMP1]], [[TMP2]] 29 ; CHECK-NEXT: call void @use(double [[TMP2]]) 44 ; CHECK-NEXT: [[TMP2:%.]] = call reassoc nnan double @llvm.sqrt.f64(double [[TMP1]]) 45 ; CHECK-NEXT: ret double [[TMP2]] 59 ; CHECK-NEXT: [[TMP2:%.]] = call double @llvm.sqrt.f64(double [[B:%.]]) 60 ; CHECK-NEXT: [[MUL:%.]] = fmul reassoc double [[TMP1]], [[TMP2]] 75 ; CHECK-NEXT: [[TMP2:%.]] = fmul reassoc nnan double [[TMP1]], [[C:%.]] [all …]
D	bit-checks.ll	7 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq i32 [[TMP1]], 3 8 ; CHECK-NEXT: [[RETVAL_0:%.]] = select i1 [[TMP2]], i32 2, i32 1 76 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], %argc 77 ; CHECK-NEXT: [[NOT_:%.]] = icmp ne i32 [[TMP2]], 0 126 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], %argc 127 ; CHECK-NEXT: [[NOT_:%.]] = icmp eq i32 [[TMP2]], 0 176 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], %argc 177 ; CHECK-NEXT: [[NOT_:%.]] = icmp ne i32 [[TMP2]], [[TMP1]] 226 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], %argc 227 ; CHECK-NEXT: [[NOT_:%.]] = icmp eq i32 [[TMP2]], [[TMP1]] [all …]
D	fast-math.ll	68 ; CHECK-NEXT: [[TMP2:%.]] = fadd reassoc double [[TMP1]], [[F1]] 69 ; CHECK-NEXT: ret double [[TMP2]] 80 ; CHECK-NEXT: [[TMP2:%.]] = fsub fast float 9.000000e+00, [[TMP1]] 81 ; CHECK-NEXT: ret float [[TMP2]] 93 ; CHECK-NEXT: [[TMP2:%.]] = fsub reassoc nsz float 9.000000e+00, [[TMP1]] 94 ; CHECK-NEXT: ret float [[TMP2]] 106 ; CHECK-NEXT: [[TMP2:%.]] = fsub float 5.000000e+00, [[F2:%.]] 107 ; CHECK-NEXT: [[TMP3:%.]] = fadd reassoc float [[TMP1]], [[TMP2]] 178 ; CHECK-NEXT: [[TMP2:%.]] = fadd reassoc float [[TMP1]], [[F1]] 179 ; CHECK-NEXT: [[TMP3:%.]] = fadd reassoc float [[TMP2]], [[F1]] [all …]
/external/pcre/dist2/src/
D	pcre2_jit_compile.c	542 #define TMP2 SLJIT_R3 macro 545 #define TMP2 SLJIT_R2 macro 1803 OP1(SLJIT_MOV, TMP2, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(offset + 1)); in init_frame() 1806 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP2, 0); in init_frame() 2159 base_reg = TMP2; in copy_recurse_data() 2169 if (base_reg != TMP2) in copy_recurse_data() 2171 status.tmp_regs[1] = TMP2; in copy_recurse_data() 2172 status.saved_tmp_regs[1] = TMP2; in copy_recurse_data() 2769 …_MOV \| SLJIT_MEM_SUPP \| SLJIT_MEM_STORE \| SLJIT_MEM_PRE, TMP1, SLJIT_MEM1(TMP2), sizeof(sljit_sw))… in do_reset_match() 2771 GET_LOCAL_BASE(TMP2, 0, OVECTOR_START + sizeof(sljit_sw)); in do_reset_match() [all …]
/external/boringssl/src/crypto/cipher_extra/asm/
D	aes128gcmsiv-x86_64.pl	`86 my $TMP2 = "%xmm3"; 97 vpclmulqdq \$0x10, $TMP0, $T, $TMP2 99 vpxor $TMP3, $TMP2, $TMP2 100 vpslldq \$8, $TMP2, $TMP3 101 vpsrldq \$8, $TMP2, $TMP2 103 vpxor $TMP2, $TMP4, $TMP4 105 vpclmulqdq \$0x10, poly(%rip), $TMP1, $TMP2 107 vpxor $TMP3, $TMP2, $TMP1 109 vpclmulqdq \$0x10, poly(%rip), $TMP1, $TMP2 111 vpxor $TMP3, $TMP2, $TMP1 [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Reassociate/
D	mulfactor.ll	38 ; CHECK-NEXT: [[TMP2:%.]] = mul i32 [[TMP1]], [[TMP1]] 39 ; CHECK-NEXT: [[TMP3:%.]] = mul i32 [[TMP2]], [[TMP2]] 56 ; CHECK-NEXT: [[TMP2:%.]] = mul i32 [[TMP1]], %x 57 ; CHECK-NEXT: [[TMP3:%.]] = mul i32 [[TMP2]], %x 58 ; CHECK-NEXT: [[F:%.]] = mul i32 [[TMP3]], [[TMP2]] 74 ; CHECK-NEXT: [[TMP2:%.]] = mul i32 [[TMP1]], %y 75 ; CHECK-NEXT: [[TMP3:%.]] = mul i32 [[TMP2]], [[TMP2]] 90 ; CHECK-NEXT: [[TMP2:%.]] = mul i32 [[TMP1]], %y 92 ; CHECK-NEXT: [[G:%.]] = mul i32 [[F]], [[TMP2]] 93 ; CHECK-NEXT: [[TMP3:%.]] = mul i32 [[G]], [[TMP2]] [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ARM/
D	vld1.ll	34 ; CHECK-NEXT: [[TMP2:%.]] = load <8 x i8>, <8 x i8> [[TMP1]], align 1 35 ; CHECK-NEXT: ret <8 x i8> [[TMP2]] 44 ; CHECK-NEXT: [[TMP2:%.]] = load <4 x i16>, <4 x i16> [[TMP1]], align 2 45 ; CHECK-NEXT: ret <4 x i16> [[TMP2]] 54 ; CHECK-NEXT: [[TMP2:%.]] = load <2 x i32>, <2 x i32> [[TMP1]], align 4 55 ; CHECK-NEXT: ret <2 x i32> [[TMP2]] 64 ; CHECK-NEXT: [[TMP2:%.]] = load <1 x i64>, <1 x i64> [[TMP1]], align 8 65 ; CHECK-NEXT: ret <1 x i64> [[TMP2]] 74 ; CHECK-NEXT: [[TMP2:%.]] = load <8 x i16>, <8 x i16> [[TMP1]], align 2 75 ; CHECK-NEXT: ret <8 x i16> [[TMP2]] [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
D	log-exp-intrinsic.ll	21 ; CHECK-NEXT: [[TMP2:%.]] = call double @llvm.log.f64(double [[TMP1]]) 22 ; CHECK-NEXT: ret double [[TMP2]] 32 ; CHECK-NEXT: [[TMP2:%.]] = call double @llvm.log.f64(double [[TMP1]]) 33 ; CHECK-NEXT: [[TMP3:%.]] = call double @llvm.exp.f64(double [[TMP2]]) 67 ; CHECK-NEXT: [[TMP2:%.]] = call double @llvm.log2.f64(double [[TMP1]]) 68 ; CHECK-NEXT: ret double [[TMP2]] 78 ; CHECK-NEXT: [[TMP2:%.]] = call double @llvm.log2.f64(double [[TMP1]]) 79 ; CHECK-NEXT: [[TMP3:%.]] = call double @llvm.exp2.f64(double [[TMP2]]) 113 ; CHECK-NEXT: [[TMP2:%.*]] = call double @llvm.exp.f64(double [[TMP1]]) 114 ; CHECK-NEXT: ret double [[TMP2]] [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
D	hsub.ll	16 ; SSE-NEXT: [[TMP2:%.]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i32 … 17 ; SSE-NEXT: [[TMP3:%.]] = fsub <2 x double> [[TMP1]], [[TMP2]] 33 ; AVX-NEXT: [[TMP2:%.]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i32 … 34 ; AVX-NEXT: [[TMP3:%.]] = fsub <2 x double> [[TMP1]], [[TMP2]] 39 ; AVX512-NEXT: [[TMP2:%.]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i… 40 ; AVX512-NEXT: [[TMP3:%.]] = fsub <2 x double> [[TMP1]], [[TMP2]] 57 ; CHECK-NEXT: [[TMP2:%.]] = shufflevector <4 x float> [[A]], <4 x float> [[B]], <4 x i32> <i32 … 58 ; CHECK-NEXT: [[TMP3:%.]] = fsub <4 x float> [[TMP1]], [[TMP2]] 83 ; SSE-NEXT: [[TMP2:%.]] = shufflevector <2 x i64> [[A]], <2 x i64> [[B]], <2 x i32> <i32 1, i32… 84 ; SSE-NEXT: [[TMP3:%.]] = sub <2 x i64> [[TMP1]], [[TMP2]] [all …]
D	hadd.ll	16 ; SSE-NEXT: [[TMP2:%.]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i32 … 17 ; SSE-NEXT: [[TMP3:%.]] = fadd <2 x double> [[TMP1]], [[TMP2]] 33 ; AVX-NEXT: [[TMP2:%.]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i32 … 34 ; AVX-NEXT: [[TMP3:%.]] = fadd <2 x double> [[TMP1]], [[TMP2]] 39 ; AVX512-NEXT: [[TMP2:%.]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i… 40 ; AVX512-NEXT: [[TMP3:%.]] = fadd <2 x double> [[TMP1]], [[TMP2]] 57 ; CHECK-NEXT: [[TMP2:%.]] = shufflevector <4 x float> [[A]], <4 x float> [[B]], <4 x i32> <i32 … 58 ; CHECK-NEXT: [[TMP3:%.]] = fadd <4 x float> [[TMP1]], [[TMP2]] 83 ; SSE-NEXT: [[TMP2:%.]] = shufflevector <2 x i64> [[A]], <2 x i64> [[B]], <2 x i32> <i32 1, i32… 84 ; SSE-NEXT: [[TMP3:%.]] = add <2 x i64> [[TMP1]], [[TMP2]] [all …]
/external/llvm/test/Transforms/InstCombine/
D	div-shift.ll	`23 ; CHECK-NEXT: [[TMP2:%.]] = lshr i64 %x, [[TMP1]] 24 ; CHECK-NEXT: ret i64 [[TMP2]] 36 ; CHECK-NEXT: [[TMP2:%.]] = zext i32 [[TMP1]] to i64 37 ; CHECK-NEXT: [[TMP3:%.]] = lshr i64 %x, [[TMP2]] 50 ; CHECK-NEXT: [[TMP2:%.]] = lshr i32 %x, [[DOTV]] 51 ; CHECK-NEXT: ret i32 [[TMP2]] 64 ; CHECK-NEXT: [[TMP2:%.*]] = select i1 %y, i32 [[TMP1]], i32 0 65 ; CHECK-NEXT: ret i32 [[TMP2]]`

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