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Searched refs:TMP3 (Results 1 – 25 of 269) sorted by relevance

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/external/boringssl/src/crypto/cipher_extra/asm/
D	aes128gcmsiv-x86_64.pl	`87 my $TMP3 = "%xmm4"; 98 vpclmulqdq \$0x01, $TMP0, $T, $TMP3 99 vpxor $TMP3, $TMP2, $TMP2 100 vpslldq \$8, $TMP2, $TMP3 102 vpxor $TMP3, $TMP1, $TMP1 106 vpshufd \$78, $TMP1, $TMP3 107 vpxor $TMP3, $TMP2, $TMP1 110 vpshufd \$78, $TMP1, $TMP3 111 vpxor $TMP3, $TMP2, $TMP1 212 my $TMP3 = "%xmm6"; [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
D	sext.ll	28 ; SLM-NEXT: [[TMP3:%.]] = sext <2 x i8> [[TMP2]] to <2 x i64> 29 ; SLM-NEXT: [[TMP4:%.]] = extractelement <2 x i64> [[TMP3]], i32 0 31 ; SLM-NEXT: [[TMP5:%.]] = extractelement <2 x i64> [[TMP3]], i32 1 39 ; AVX-NEXT: [[TMP3:%.]] = sext <2 x i8> [[TMP2]] to <2 x i64> 40 ; AVX-NEXT: [[TMP4:%.]] = extractelement <2 x i64> [[TMP3]], i32 0 42 ; AVX-NEXT: [[TMP5:%.]] = extractelement <2 x i64> [[TMP3]], i32 1 81 ; SLM-NEXT: [[TMP3:%.]] = sext <4 x i8> [[TMP2]] to <4 x i32> 82 ; SLM-NEXT: [[TMP4:%.]] = extractelement <4 x i32> [[TMP3]], i32 0 84 ; SLM-NEXT: [[TMP5:%.]] = extractelement <4 x i32> [[TMP3]], i32 1 86 ; SLM-NEXT: [[TMP6:%.]] = extractelement <4 x i32> [[TMP3]], i32 2 [all …]
D	zext.ll	28 ; SLM-NEXT: [[TMP3:%.]] = zext <2 x i8> [[TMP2]] to <2 x i64> 29 ; SLM-NEXT: [[TMP4:%.]] = extractelement <2 x i64> [[TMP3]], i32 0 31 ; SLM-NEXT: [[TMP5:%.]] = extractelement <2 x i64> [[TMP3]], i32 1 39 ; AVX-NEXT: [[TMP3:%.]] = zext <2 x i8> [[TMP2]] to <2 x i64> 40 ; AVX-NEXT: [[TMP4:%.]] = extractelement <2 x i64> [[TMP3]], i32 0 42 ; AVX-NEXT: [[TMP5:%.]] = extractelement <2 x i64> [[TMP3]], i32 1 63 ; CHECK-NEXT: [[TMP3:%.]] = zext <4 x i8> [[TMP2]] to <4 x i32> 64 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <4 x i32> [[TMP3]], i32 0 66 ; CHECK-NEXT: [[TMP5:%.]] = extractelement <4 x i32> [[TMP3]], i32 1 68 ; CHECK-NEXT: [[TMP6:%.]] = extractelement <4 x i32> [[TMP3]], i32 2 [all …]
D	hsub.ll	17 ; SSE-NEXT: [[TMP3:%.]] = fsub <2 x double> [[TMP1]], [[TMP2]] 18 ; SSE-NEXT: ret <2 x double> [[TMP3]] 34 ; AVX-NEXT: [[TMP3:%.]] = fsub <2 x double> [[TMP1]], [[TMP2]] 35 ; AVX-NEXT: ret <2 x double> [[TMP3]] 40 ; AVX512-NEXT: [[TMP3:%.]] = fsub <2 x double> [[TMP1]], [[TMP2]] 41 ; AVX512-NEXT: ret <2 x double> [[TMP3]] 58 ; CHECK-NEXT: [[TMP3:%.]] = fsub <4 x float> [[TMP1]], [[TMP2]] 59 ; CHECK-NEXT: ret <4 x float> [[TMP3]] 84 ; SSE-NEXT: [[TMP3:%.*]] = sub <2 x i64> [[TMP1]], [[TMP2]] 85 ; SSE-NEXT: ret <2 x i64> [[TMP3]] [all …]
D	hadd.ll	17 ; SSE-NEXT: [[TMP3:%.]] = fadd <2 x double> [[TMP1]], [[TMP2]] 18 ; SSE-NEXT: ret <2 x double> [[TMP3]] 34 ; AVX-NEXT: [[TMP3:%.]] = fadd <2 x double> [[TMP1]], [[TMP2]] 35 ; AVX-NEXT: ret <2 x double> [[TMP3]] 40 ; AVX512-NEXT: [[TMP3:%.]] = fadd <2 x double> [[TMP1]], [[TMP2]] 41 ; AVX512-NEXT: ret <2 x double> [[TMP3]] 58 ; CHECK-NEXT: [[TMP3:%.]] = fadd <4 x float> [[TMP1]], [[TMP2]] 59 ; CHECK-NEXT: ret <4 x float> [[TMP3]] 84 ; SSE-NEXT: [[TMP3:%.*]] = add <2 x i64> [[TMP1]], [[TMP2]] 85 ; SSE-NEXT: ret <2 x i64> [[TMP3]] [all …]
D	extractelement.ll	`12 ; CHECK-NEXT: [[TMP3:%.]] = extractelement <2 x float> [[TMP1]], i32 1 13 ; CHECK-NEXT: [[ADD:%.]] = fadd float [[TMP2]], [[TMP3]] 28 ; THRESH2-NEXT: [[TMP3:%.]] = extractelement <2 x float> [[TMP2]], i32 0 30 ; THRESH2-NEXT: [[ADD:%.]] = fadd float [[TMP3]], [[TMP4]] 47 ; THRESH1-NEXT: [[TMP3:%.]] = insertelement <2 x float> [[TMP2]], float [[TMP1]], i32 1 48 ; THRESH1-NEXT: [[TMP4:%.]] = fmul <2 x float> [[X]], [[TMP3]]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
D	select-of-bittest.ll	102 ; CHECK-NEXT: [[TMP3:%.]] = zext i1 [[TMP2]] to i32 103 ; CHECK-NEXT: ret i32 [[TMP3]] 116 ; CHECK-NEXT: [[TMP3:%.]] = zext <2 x i1> [[TMP2]] to <2 x i32> 117 ; CHECK-NEXT: ret <2 x i32> [[TMP3]] 130 ; CHECK-NEXT: [[TMP3:%.]] = zext <2 x i1> [[TMP2]] to <2 x i32> 131 ; CHECK-NEXT: ret <2 x i32> [[TMP3]] 144 ; CHECK-NEXT: [[TMP3:%.]] = zext <3 x i1> [[TMP2]] to <3 x i32> 145 ; CHECK-NEXT: ret <3 x i32> [[TMP3]] 162 ; CHECK-NEXT: [[TMP3:%.]] = icmp ne i32 [[TMP2]], 0 163 ; CHECK-NEXT: [[TMP5:%.]] = zext i1 [[TMP3]] to i32 [all …]
D	unsigned_saturated_sub.ll	`17 ; CHECK-NEXT: [[TMP3:%.]] = sub i64 [[TMP2]], [[B]] 18 ; CHECK-NEXT: ret i64 [[TMP3]] 32 ; CHECK-NEXT: [[TMP3:%.]] = sub i64 [[TMP2]], [[B]] 33 ; CHECK-NEXT: ret i64 [[TMP3]] 48 ; CHECK-NEXT: [[TMP3:%.]] = sub <4 x i32> [[TMP2]], [[B]] 49 ; CHECK-NEXT: ret <4 x i32> [[TMP3]] 64 ; CHECK-NEXT: [[TMP3:%.]] = sub i64 [[TMP2]], [[B]] 67 ; CHECK-NEXT: ret i64 [[TMP3]] 83 ; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP2]], [[B]] 86 ; CHECK-NEXT: ret i64 [[TMP3]] [all …]`
D	select-bitext-bitwise-ops.ll	8 ; CHECK-NEXT: [[TMP3:%.]] = icmp eq i32 [[TMP1]], 0 9 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] 27 ; CHECK-NEXT: [[TMP3:%.]] = zext i32 [[TMP2]] to i64 28 ; CHECK-NEXT: [[TMP4:%.]] = ashr i64 [[Y:%.]], [[TMP3]] 44 ; CHECK-NEXT: [[TMP3:%.]] = icmp eq i32 [[TMP1]], 0 45 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] 63 ; CHECK-NEXT: [[TMP3:%.]] = zext i32 [[TMP2]] to i64 64 ; CHECK-NEXT: [[TMP4:%.]] = ashr i64 [[Y:%.]], [[TMP3]] 80 ; CHECK-NEXT: [[TMP3:%.]] = icmp eq i32 [[TMP1]], 0 81 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] [all …]
D	or-shifted-masks.ll	7 ; CHECK-NEXT: [[TMP3:%.]] = shl i32 %x, 5 8 ; CHECK-NEXT: [[TMP4:%.]] = and i32 [[TMP3]], 32 24 ; CHECK-NEXT: [[TMP3:%.]] = lshr i32 %x, 4 25 ; CHECK-NEXT: [[TMP4:%.]] = and i32 [[TMP3]], 7 41 ; CHECK-NEXT: [[TMP3:%.]] = shl i32 %x, 2 42 ; CHECK-NEXT: [[TMP4:%.]] = and i32 [[TMP3]], 28 58 ; CHECK-NEXT: [[TMP3:%.]] = lshr i32 %x, 1 59 ; CHECK-NEXT: [[TMP4:%.]] = and i32 [[TMP3]], 3 79 ; CHECK-NEXT: [[TMP3:%.]] = shl i32 %x, 8 80 ; CHECK-NEXT: [[TMP4:%.]] = and i32 [[TMP3]], 24576 [all …]
D	pow-4.ll	45 ; CHECK-NEXT: [[TMP3:%.]] = fmul fast double [[TMP2]], [[TMP2]] 46 ; CHECK-NEXT: [[TMP4:%.]] = fmul fast double [[TMP3]], [[TMP3]] 59 ; CHECK-NEXT: [[TMP3:%.]] = fmul fast double [[TMP2]], [[X]] 60 ; CHECK-NEXT: [[TMP4:%.]] = fmul fast double [[TMP1]], [[TMP3]] 73 ; CHECK-NEXT: [[TMP3:%.]] = fmul fast double [[TMP2]], [[TMP2]] 74 ; CHECK-NEXT: [[TMP4:%.]] = fmul fast double [[TMP3]], [[TMP3]] 99 ; CHECK-NEXT: [[TMP3:%.]] = fmul fast double [[TMP2]], [[TMP2]] 100 ; CHECK-NEXT: [[TMP4:%.]] = fmul fast double [[TMP3]], [[TMP3]]
D	icmp-logical.ll	222 ; CHECK-NEXT: [[TMP3:%.]] = and i32 [[X]], 3 223 ; CHECK-NEXT: [[TMP4:%.]] = icmp eq i32 [[TMP3]], 1 255 ; CHECK-NEXT: [[TMP3:%.]] = and i32 [[X]], 3 256 ; CHECK-NEXT: [[TMP4:%.]] = icmp eq i32 [[TMP3]], 1 301 ; CHECK-NEXT: [[TMP3:%.]] = and i32 [[X]], 3 302 ; CHECK-NEXT: [[TMP4:%.]] = icmp eq i32 [[TMP3]], 0 317 ; CHECK-NEXT: [[TMP3:%.]] = and i32 [[X:%.]], 15 318 ; CHECK-NEXT: [[TMP4:%.]] = icmp eq i32 [[TMP3]], 8 332 ; CHECK-NEXT: [[TMP3:%.]] = and i32 [[X:%.]], 15 333 ; CHECK-NEXT: [[TMP4:%.]] = icmp eq i32 [[TMP3]], 8 [all …]
D	select-obo-peo-ops.ll	8 ; CHECK-NEXT: [[TMP3:%.]] = icmp eq i32 [[TMP1]], 0 9 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] 27 ; CHECK-NEXT: [[TMP3:%.]] = icmp eq i32 [[TMP1]], 0 28 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] 46 ; CHECK-NEXT: [[TMP3:%.]] = icmp eq i32 [[TMP1]], 0 47 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] 65 ; CHECK-NEXT: [[TMP3:%.]] = icmp eq i32 [[TMP1]], 0 66 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] 84 ; CHECK-NEXT: [[TMP3:%.]] = icmp eq i32 [[TMP1]], 0 85 ; CHECK-NEXT: [[NARROW:%.]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] [all …]
D	select-icmp-and.ll	114 ; CHECK-NEXT: [[TMP3:%.]] = select i1 [[TMP2]], i32 42, i32 40 115 ; CHECK-NEXT: ret i32 [[TMP3]] 127 ; CHECK-NEXT: [[TMP3:%.]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i3… 128 ; CHECK-NEXT: ret <2 x i32> [[TMP3]] 140 ; CHECK-NEXT: [[TMP3:%.]] = select i1 [[TMP2]], i32 42, i32 40 141 ; CHECK-NEXT: ret i32 [[TMP3]] 153 ; CHECK-NEXT: [[TMP3:%.]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i3… 154 ; CHECK-NEXT: ret <2 x i32> [[TMP3]] 167 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, … 168 ; CHECK-NEXT: ret <2 x i32> [[TMP3]] [all …]
D	and-or.ll	`7 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 8 ; CHECK-NEXT: ret i32 [[TMP3]] 20 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 21 ; CHECK-NEXT: ret i32 [[TMP3]] 33 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 34 ; CHECK-NEXT: ret i32 [[TMP3]] 46 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 47 ; CHECK-NEXT: ret i32 [[TMP3]]`
/external/llvm/test/Transforms/InstCombine/
D	and-or.ll	`7 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 8 ; CHECK-NEXT: ret i32 [[TMP3]] 20 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 21 ; CHECK-NEXT: ret i32 [[TMP3]] 33 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 34 ; CHECK-NEXT: ret i32 [[TMP3]] 46 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 47 ; CHECK-NEXT: ret i32 [[TMP3]]`
D	x86-sse2.ll	9 ; CHECK-NEXT: [[TMP3:%.]] = extractelement <2 x double> [[TMP2]], i32 0 10 ; CHECK-NEXT: ret double [[TMP3]] 192 ; CHECK-NEXT: [[TMP3:%.]] = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[TMP1]],… 193 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <2 x double> [[TMP3]], i32 0 232 ; CHECK-NEXT: [[TMP3:%.]] = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[TMP1]],… 233 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <2 x double> [[TMP3]], i32 0 272 ; CHECK-NEXT: [[TMP3:%.]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]],… 273 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <2 x double> [[TMP3]], i32 0 302 ; CHECK-NEXT: [[TMP3:%.]] = tail call i32 @llvm.x86.sse2.comieq.sd(<2 x double> [[TMP1]], <2 x … 303 ; CHECK-NEXT: ret i32 [[TMP3]] [all …]
D	x86-sse.ll	9 ; CHECK-NEXT: [[TMP3:%.]] = extractelement <4 x float> [[TMP2]], i32 0 10 ; CHECK-NEXT: ret float [[TMP3]] 38 ; CHECK-NEXT: [[TMP3:%.]] = extractelement <4 x float> [[TMP2]], i32 0 39 ; CHECK-NEXT: ret float [[TMP3]] 67 ; CHECK-NEXT: [[TMP3:%.]] = extractelement <4 x float> [[TMP2]], i32 0 68 ; CHECK-NEXT: ret float [[TMP3]] 284 ; CHECK-NEXT: [[TMP3:%.]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP1]], <4… 285 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <4 x float> [[TMP3]], i32 0 331 ; CHECK-NEXT: [[TMP3:%.]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP1]], <4… 332 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0 [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Reassociate/
D	mulfactor.ll	39 ; CHECK-NEXT: [[TMP3:%.]] = mul i32 [[TMP2]], [[TMP2]] 40 ; CHECK-NEXT: ret i32 [[TMP3]] 57 ; CHECK-NEXT: [[TMP3:%.]] = mul i32 [[TMP2]], %x 58 ; CHECK-NEXT: [[F:%.]] = mul i32 [[TMP3]], [[TMP2]] 75 ; CHECK-NEXT: [[TMP3:%.]] = mul i32 [[TMP2]], [[TMP2]] 76 ; CHECK-NEXT: ret i32 [[TMP3]] 93 ; CHECK-NEXT: [[TMP3:%.]] = mul i32 [[G]], [[TMP2]] 94 ; CHECK-NEXT: [[H:%.]] = mul i32 [[TMP3]], %z 113 ; CHECK-NEXT: [[TMP3:%.]] = mul i32 [[TMP2]], %z 114 ; CHECK-NEXT: [[TMP4:%.]] = mul i32 [[TMP3]], %y [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/
D	x86-sse2.ll	150 ; CHECK-NEXT: [[TMP3:%.]] = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[TMP1]],… 151 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <2 x double> [[TMP3]], i32 0 190 ; CHECK-NEXT: [[TMP3:%.]] = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[TMP1]],… 191 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <2 x double> [[TMP3]], i32 0 230 ; CHECK-NEXT: [[TMP3:%.]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]],… 231 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <2 x double> [[TMP3]], i32 0 260 ; CHECK-NEXT: [[TMP3:%.]] = tail call i32 @llvm.x86.sse2.comieq.sd(<2 x double> [[TMP1]], <2 x … 261 ; CHECK-NEXT: ret i32 [[TMP3]] 275 ; CHECK-NEXT: [[TMP3:%.]] = tail call i32 @llvm.x86.sse2.comige.sd(<2 x double> [[TMP1]], <2 x … 276 ; CHECK-NEXT: ret i32 [[TMP3]] [all …]
D	x86-sse.ll	9 ; CHECK-NEXT: [[TMP3:%.]] = extractelement <4 x float> [[TMP2]], i32 0 10 ; CHECK-NEXT: ret float [[TMP3]] 65 ; CHECK-NEXT: [[TMP3:%.]] = extractelement <4 x float> [[TMP2]], i32 0 66 ; CHECK-NEXT: ret float [[TMP3]] 234 ; CHECK-NEXT: [[TMP3:%.]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP1]], <4… 235 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <4 x float> [[TMP3]], i32 0 281 ; CHECK-NEXT: [[TMP3:%.]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP1]], <4… 282 ; CHECK-NEXT: [[TMP4:%.]] = extractelement <4 x float> [[TMP3]], i32 0 328 ; CHECK-NEXT: [[TMP3:%.]] = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[TMP1]], <4… 329 ; CHECK-NEXT: [[R:%.]] = extractelement <4 x float> [[TMP3]], i32 0 [all …]
D	x86-avx512.ll	11 ; CHECK-NEXT: [[TMP3:%.]] = fadd float [[TMP1]], [[TMP2]] 12 ; CHECK-NEXT: [[TMP4:%.]] = insertelement <4 x float> [[A]], float [[TMP3]], i64 0 38 ; CHECK-NEXT: [[TMP3:%.]] = fadd float [[TMP1]], [[TMP2]] 42 ; CHECK-NEXT: [[TMP7:%.]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP6]] 88 ; CHECK-NEXT: [[TMP3:%.]] = fadd double [[TMP1]], [[TMP2]] 89 ; CHECK-NEXT: [[TMP4:%.]] = insertelement <2 x double> [[A]], double [[TMP3]], i64 0 111 ; CHECK-NEXT: [[TMP3:%.]] = fadd double [[TMP1]], [[TMP2]] 115 ; CHECK-NEXT: [[TMP7:%.]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP6]] 153 ; CHECK-NEXT: [[TMP3:%.]] = fsub float [[TMP1]], [[TMP2]] 154 ; CHECK-NEXT: [[TMP4:%.]] = insertelement <4 x float> [[A]], float [[TMP3]], i64 0 [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/ExpandMemCmp/X86/
D	memcmp.ll	12 ; ALL-NEXT: [[TMP3:%.]] = load i16, i16 [[TMP1]] 14 ; ALL-NEXT: [[TMP5:%.]] = call i16 @llvm.bswap.i16(i16 [[TMP3]]) 35 ; ALL-NEXT: [[TMP3:%.]] = bitcast i8* [[X:%.]] to i16 37 ; ALL-NEXT: [[TMP5:%.]] = load i16, i16 [[TMP3]] 64 ; ALL-NEXT: [[TMP3:%.]] = load i32, i32 [[TMP1]] 66 ; ALL-NEXT: [[TMP5:%.]] = call i32 @llvm.bswap.i32(i32 [[TMP3]]) 89 ; ALL-NEXT: [[TMP3:%.]] = bitcast i8* [[X:%.]] to i32 91 ; ALL-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP3]] 124 ; ALL-NEXT: [[TMP3:%.]] = bitcast i8 [[X:%.]] to i32 126 ; ALL-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP3]] [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/NewGVN/
D	storeoverstore.ll	`13 ; CHECK-NEXT: [[TMP3:%.]] = icmp ne i32 [[TMP1:%.]], 0 14 ; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.]], label [[TMP5:%.]] 18 ; CHECK-NEXT: br i1 [[TMP3]], label [[TMP6:%.]], label [[TMP7:%.]] 53 ; CHECK-NEXT: [[TMP3:%.]] = icmp ne i32 [[TMP1:%.]], 0 54 ; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.]], label [[TMP5:%.]] 59 ; CHECK-NEXT: br i1 [[TMP3]], label [[TMP7:%.]], label [[TMP8:%.]]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/AggressiveInstCombine/
D	masked-cmp.ll	`10 ; CHECK-NEXT: [[TMP3:%.]] = zext i1 [[TMP2]] to i32 11 ; CHECK-NEXT: ret i32 [[TMP3]] 23 ; CHECK-NEXT: [[TMP3:%.]] = zext i1 [[TMP2]] to i32 24 ; CHECK-NEXT: ret i32 [[TMP3]] 42 ; CHECK-NEXT: [[TMP3:%.]] = zext i1 [[TMP2]] to i32 43 ; CHECK-NEXT: ret i32 [[TMP3]] 60 ; CHECK-NEXT: [[TMP3:%.]] = zext i1 [[TMP2]] to i32 61 ; CHECK-NEXT: ret i32 [[TMP3]] 73 ; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64 74 ; CHECK-NEXT: ret i64 [[TMP3]] [all …]`

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