Home
last modified time | relevance | path

Searched refs:TRI (Results 1 – 25 of 909) sorted by relevance

12345678910>>...37

/external/llvm/include/llvm/CodeGen/
DLivePhysRegs.h44 const TargetRegisterInfo *TRI; variable
51 LivePhysRegs() : TRI(nullptr), LiveRegs() {} in LivePhysRegs()
54 LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) { in LivePhysRegs() argument
55 assert(TRI && "Invalid TargetRegisterInfo pointer."); in LivePhysRegs()
56 LiveRegs.setUniverse(TRI->getNumRegs()); in LivePhysRegs()
60 void init(const TargetRegisterInfo *TRI) { in init() argument
61 assert(TRI && "Invalid TargetRegisterInfo pointer."); in init()
62 this->TRI = TRI; in init()
64 LiveRegs.setUniverse(TRI->getNumRegs()); in init()
75 assert(TRI && "LivePhysRegs is not initialized."); in addReg()
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp115 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { in hasVGPROperands() argument
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
130 const SIRegisterInfo &TRI, in getCopyRegClasses() argument
138 TRI.getPhysRegClass(SrcReg); in getCopyRegClasses()
146 TRI.getPhysRegClass(DstReg); in getCopyRegClasses()
153 const SIRegisterInfo &TRI) { in isVGPRToSGPRCopy() argument
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
159 const SIRegisterInfo &TRI) { in isSGPRToVGPRCopy() argument
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
177 const SIRegisterInfo *TRI, in foldVGPRCopyIntoRegSequence() argument
[all …]
DSIFrameLowering.cpp64 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in emitPrologue() local
75 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue( in emitPrologue()
80 PreloadedPrivateBufferReg = TRI->getPreloadedValue( in emitPrologue()
100 = TRI->getPreloadedValue(MF, SIRegisterInfo::FLAT_SCRATCH_INIT); in emitPrologue()
106 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitPrologue()
110 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitPrologue()
155 if (ScratchRsrcReg == TRI->reservedPrivateSegmentBufferReg(MF)) { in emitPrologue()
174 if (ScratchWaveOffsetReg == TRI->reservedPrivateSegmentWaveByteOffsetReg(MF)) { in emitPrologue()
196 TRI->isSubRegisterEq(ScratchRsrcReg, Reg)) in emitPrologue()
209 assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg)); in emitPrologue()
[all …]
DR600ExpandSpecialInstrs.cpp71 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
179 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
200 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
203 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
206 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
231 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
286 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction()
[all …]
/external/llvm/lib/CodeGen/
DRegisterClassInfo.cpp33 : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {} in RegisterClassInfo()
40 if (MF->getSubtarget().getRegisterInfo() != TRI) { in runOnMachineFunction()
41 TRI = MF->getSubtarget().getRegisterInfo(); in runOnMachineFunction()
42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
43 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction()
50 assert(TRI && "no register info set"); in runOnMachineFunction()
51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction()
56 CSRNum.resize(TRI->getNumRegs(), 0); in runOnMachineFunction()
58 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
103 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
[all …]
DTargetRegisterInfo.cpp45 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, in PrintReg() argument
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { in PrintReg()
54 else if (TRI && Reg < TRI->getNumRegs()) in PrintReg()
55 OS << '%' << TRI->getName(Reg); in PrintReg()
59 if (TRI) in PrintReg()
60 OS << ':' << TRI->getSubRegIndexName(SubIdx); in PrintReg()
67 Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { in PrintRegUnit() argument
68 return Printable([Unit, TRI](raw_ostream &OS) { in PrintRegUnit()
70 if (!TRI) { in PrintRegUnit()
76 if (Unit >= TRI->getNumRegUnits()) { in PrintRegUnit()
[all …]
DLiveRegMatrix.cpp50 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction()
54 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction()
74 bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, in foreachUnit() argument
77 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
99 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign()
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign()
105 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); in assign()
116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
[all …]
DAggressiveAntiDepBreaker.cpp118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in AggressiveAntiDepBreaker()
123 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
133 dbgs() << " " << TRI->getName(r)); in AggressiveAntiDepBreaker()
143 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); in StartBlock()
153 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
166 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { in StartBlock()
169 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
197 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
206 dbgs() << " " << TRI->getName(Reg) << "=g" << in Observe()
243 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs()
[all …]
DRegisterScavenging.cpp35 for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) { in setRegUsed()
66 TRI = MF.getSubtarget().getRegisterInfo(); in enterBasicBlock()
69 assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) && in enterBasicBlock()
79 NumRegUnits = TRI->getNumRegUnits(); in enterBasicBlock()
93 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
110 for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) { in determineKillsAndDefs()
111 for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) { in determineKillsAndDefs()
211 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in forward()
217 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { in forward()
236 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && in forward()
[all …]
/external/llvm/lib/CodeGen/AsmPrinter/
DDwarfExpression.cpp68 bool DwarfExpression::AddMachineRegIndirect(const TargetRegisterInfo &TRI, in AddMachineRegIndirect() argument
70 if (isFrameRegister(TRI, MachineReg)) { in AddMachineRegIndirect()
77 int DwarfReg = TRI.getDwarfRegNum(MachineReg, false); in AddMachineRegIndirect()
85 bool DwarfExpression::AddMachineRegPiece(const TargetRegisterInfo &TRI, in AddMachineRegPiece() argument
89 if (!TRI.isPhysicalRegister(MachineReg)) in AddMachineRegPiece()
92 int Reg = TRI.getDwarfRegNum(MachineReg, false); in AddMachineRegPiece()
104 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { in AddMachineRegPiece()
105 Reg = TRI.getDwarfRegNum(*SR, false); in AddMachineRegPiece()
107 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); in AddMachineRegPiece()
108 unsigned Size = TRI.getSubRegIdxSize(Idx); in AddMachineRegPiece()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp147 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { in hasVGPROperands() argument
154 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
162 const SIRegisterInfo &TRI, in getCopyRegClasses() argument
170 TRI.getPhysRegClass(SrcReg); in getCopyRegClasses()
178 TRI.getPhysRegClass(DstReg); in getCopyRegClasses()
185 const SIRegisterInfo &TRI) { in isVGPRToSGPRCopy() argument
186 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
191 const SIRegisterInfo &TRI) { in isSGPRToVGPRCopy() argument
192 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
196 const SIRegisterInfo *TRI, in tryChangeVGPRtoSGPRinCopy() argument
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DLivePhysRegs.h50 const TargetRegisterInfo *TRI = nullptr; variable
58 LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) { in LivePhysRegs() argument
59 LiveRegs.setUniverse(TRI.getNumRegs()); in LivePhysRegs()
66 void init(const TargetRegisterInfo &TRI) { in init() argument
67 this->TRI = &TRI; in init()
69 LiveRegs.setUniverse(TRI.getNumRegs()); in init()
80 assert(TRI && "LivePhysRegs is not initialized."); in addReg()
81 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); in addReg()
82 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in addReg()
90 assert(TRI && "LivePhysRegs is not initialized."); in removeReg()
[all …]
DLiveRegUnits.h32 const TargetRegisterInfo *TRI = nullptr; variable
40 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits() argument
41 init(TRI); in LiveRegUnits()
51 const TargetRegisterInfo *TRI) { in accumulateUsedDefed() argument
64 if (!TRI->isConstantPhysReg(Reg)) in accumulateUsedDefed()
75 void init(const TargetRegisterInfo &TRI) { in init() argument
76 this->TRI = &TRI; in init()
78 Units.resize(TRI.getNumRegUnits()); in init()
89 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) in addReg()
96 for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) { in addRegMasked()
[all …]
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp24 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify()
26 assert(ContainedRegClasses.size() == TRI.getNumRegClasses() && in verify()
28 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify()
29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
40 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
75 void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
76 print(dbgs(), /* IsForDebug */ true, TRI); in dump()
80 const TargetRegisterInfo *TRI) const { in print()
90 if (!TRI || ContainedRegClasses.empty()) in print()
92 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && in print()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp31 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify()
33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify()
34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
81 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
82 print(dbgs(), /* IsForDebug */ true, TRI); in dump()
87 const TargetRegisterInfo *TRI) const { in print()
97 if (!TRI || ContainedRegClasses.empty()) in print()
99 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && in print()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegisterClassInfo.cpp49 if (MF->getSubtarget().getRegisterInfo() != TRI) { in runOnMachineFunction()
50 TRI = MF->getSubtarget().getRegisterInfo(); in runOnMachineFunction()
51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
56 assert(TRI && "no register info set"); in runOnMachineFunction()
63 CalleeSavedAliases.resize(TRI->getNumRegs(), 0); in runOnMachineFunction()
65 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
81 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction()
115 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
134 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
147 TRI->getLargestLegalSuperClass(RC, *MF)) in compute()
[all …]
DTargetRegisterInfo.cpp89 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI, in printReg() argument
91 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
104 else if (!TRI) in printReg()
106 else if (Reg < TRI->getNumRegs()) { in printReg()
108 printLowerCase(TRI->getName(Reg), OS); in printReg()
113 if (TRI) in printReg()
114 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg()
121 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { in printRegUnit() argument
122 return Printable([Unit, TRI](raw_ostream &OS) { in printRegUnit()
124 if (!TRI) { in printRegUnit()
[all …]
DLiveRegMatrix.cpp56 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction()
60 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction()
80 static bool foreachUnit(const TargetRegisterInfo *TRI, in foreachUnit() argument
84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " in assign()
106 << printReg(PhysReg, TRI) << ':'); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
112 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); in assign()
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from " in unassign()
[all …]
DAggressiveAntiDepBreaker.cpp131 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
135 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
145 << " " << printReg(r, TRI)); in AggressiveAntiDepBreaker()
155 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); in StartBlock()
165 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
183 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
211 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
220 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe()
257 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs()
315 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in HandleLastUse()
[all …]
DRegisterScavenging.cpp60 TRI = MF.getSubtarget().getRegisterInfo(); in init()
62 LiveUnits.init(*TRI); in init()
64 assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) && in init()
69 NumRegUnits = TRI->getNumRegUnits(); in init()
101 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
106 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in removeRegUnits()
123 for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) { in determineKillsAndDefs()
124 for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) { in determineKillsAndDefs()
224 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in forward()
230 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { in forward()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DVirtRegRewriter.cpp69 const TargetRegisterInfo &TRI) { in substitutePhysReg() argument
71 MO.substPhysReg(Reg, TRI); in substitutePhysReg()
80 MI.addRegisterKilled(Reg, &TRI, /*AddIfNotFound=*/ true); in substitutePhysReg()
160 const TargetRegisterInfo *TRI; member in __anond254b4590311::AvailableSpills
179 : TRI(tri), TII(tii) { in AvailableSpills()
188 const TargetRegisterInfo *getRegInfo() const { return TRI; } in getRegInfo()
219 DEBUG(dbgs() << " in physreg " << TRI->getName(Reg) in addAvailable()
289 const TargetRegisterInfo *TRI, in ComputeReloadLoc() argument
327 for (const unsigned *Alias = TRI->getAliasSet(PhysReg); *Alias; ++Alias) in ComputeReloadLoc()
473 static void ResurrectConfirmedKill(unsigned Reg, const TargetRegisterInfo* TRI, in ResurrectConfirmedKill() argument
[all …]
DRegisterScavenging.cpp40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in setUsed()
48 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R) in isAliasUsed()
83 TRI = TM.getRegisterInfo(); in enterBasicBlock()
86 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && in enterBasicBlock()
91 NumPhysRegs = TRI->getNumRegs(); in enterBasicBlock()
95 ReservedRegs = TRI->getReservedRegs(MF); in enterBasicBlock()
99 const unsigned *CSRegs = TRI->getCalleeSavedRegs(); in enterBasicBlock()
113 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) in addRegWithSubRegs()
119 for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++) in addRegWithAliases()
202 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in forward()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsOptionRecord.h47 const MCRegisterInfo *TRI = Context.getRegisterInfo(); in MipsRegInfoRecord() local
48 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
49 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
50 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
51 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
52 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
53 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
54 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
55 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
56 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/external/llvm/lib/Target/Mips/
DMipsOptionRecord.h45 const MCRegisterInfo *TRI = Context.getRegisterInfo(); in MipsRegInfoRecord() local
46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
52 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
53 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
54 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp40 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createLRSpillSlot() local
44 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
46 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
47 TRI.getSpillAlignment(RC), true); in createLRSpillSlot()
58 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createFPSpillSlot() local
60 FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createFPSpillSlot()
61 TRI.getSpillAlignment(RC), true); in createFPSpillSlot()
71 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createEHSpillSlot() local
73 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
74 unsigned Align = TRI.getSpillAlignment(RC); in createEHSpillSlot()

12345678910>>...37