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Searched refs:TmpR1 (Results 1 – 4 of 4) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.cpp1641 unsigned TmpR1 = MRI.createVirtualRegister(RC); in expandStoreVecPred() local
1646 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1) in expandStoreVecPred()
1651 HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI); in expandStoreVecPred()
1655 NewRegs.push_back(TmpR1); in expandStoreVecPred()
1676 unsigned TmpR1 = MRI.createVirtualRegister(RC); in expandLoadVecPred() local
1682 HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI); in expandLoadVecPred()
1686 .addReg(TmpR1, RegState::Kill) in expandLoadVecPred()
1690 NewRegs.push_back(TmpR1); in expandLoadVecPred()
DHexagonSplitDouble.cpp957 unsigned TmpR1 = MRI->createVirtualRegister(IntRC); in splitAslOr() local
958 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR1) in splitAslOr()
965 .addReg(TmpR1); in splitAslOr()
/external/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.cpp1481 unsigned TmpR1 = MRI.createVirtualRegister(RC); in expandStoreVecPred() local
1487 BuildMI(B, It, DL, HII.get(VandOpc), TmpR1) in expandStoreVecPred()
1492 HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI); in expandStoreVecPred()
1496 NewRegs.push_back(TmpR1); in expandStoreVecPred()
1520 unsigned TmpR1 = MRI.createVirtualRegister(RC); in expandLoadVecPred() local
1525 HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI); in expandLoadVecPred()
1530 .addReg(TmpR1, RegState::Kill) in expandLoadVecPred()
1534 NewRegs.push_back(TmpR1); in expandLoadVecPred()
DHexagonSplitDouble.cpp916 unsigned TmpR1 = MRI->createVirtualRegister(IntRC); in splitAslOr() local
917 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR1) in splitAslOr()
924 .addReg(TmpR1); in splitAslOr()