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Searched refs:VDUPLANE (Results 1 – 11 of 11) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.h151 VDUPLANE, enumerator
DARMISelLowering.cpp903 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; in getTargetNodeName()
4281 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, in GeneratePerfectShuffle()
4353 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, in LowerVECTOR_SHUFFLE()
7319 if (User->getOpcode() != ARMISD::VDUPLANE || in CombineVLDDUP()
7942 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); in PerformDAGCombine()
DARMInstrNEON.td120 // VDUPLANE can produce a quad-register result from a double-register source,
122 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc5303 /* 10793*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
5362 /* 10923*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
5387 /* 10972*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
5408 /* 11014*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
5432 /* 11062*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
5453 /* 11104*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
5479 /* 11153*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
5500 /* 11194*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
5526 /* 11242*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
5551 /* 11290*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
[all …]
DARMGenFastISel.inc4847 // FastEmit functions for ARMISD::VDUPLANE.
5751 case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri(VT, RetVT, Op0, Op0IsKill, imm1);
6692 // FastEmit functions for ARMISD::VDUPLANE.
6734 …case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(VT, RetVT, Op0, …
/external/llvm/lib/Target/ARM/
DARMISelLowering.h149 VDUPLANE, enumerator
DARMISelLowering.cpp1206 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; in getTargetNodeName()
5762 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
5767 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
6154 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, in GeneratePerfectShuffle()
6255 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, in LowerVECTOR_SHUFFLE()
10149 if (User->getOpcode() != ARMISD::VDUPLANE || in CombineVLDDUP()
11048 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); in PerformDAGCombine()
DARMInstrNEON.td563 // VDUPLANE can produce a quad-register result from a double-register source,
565 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.h181 VDUPLANE, enumerator
DARMISelLowering.cpp1335 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; in getTargetNodeName()
6573 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
6578 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
6979 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, in GeneratePerfectShuffle()
7080 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, in LowerVECTOR_SHUFFLE()
11782 if (User->getOpcode() != ARMISD::VDUPLANE || in CombineVLDDUP()
12772 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); in PerformDAGCombine()
DARMInstrNEON.td553 // VDUPLANE can produce a quad-register result from a double-register source,
555 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",