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Searched refs:VEC2PREFSLOT (Results 1 – 5 of 5) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.h43 VEC2PREFSLOT, ///< Extract element 0 enumerator
DSPUISelLowering.cpp481 node_names[(unsigned) SPUISD::VEC2PREFSLOT] = "SPUISD::VEC2PREFSLOT"; in getTargetNodeName()
677 result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, in LowerLOAD()
721 result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, result ); in LowerLOAD()
1099 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, in LowerConstantFP()
2015 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N); in LowerEXTRACT_VECTOR_ELT()
2080 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, in LowerEXTRACT_VECTOR_ELT()
2148 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, in LowerEXTRACT_VECTOR_ELT()
2698 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, truncShuffle); in LowerTRUNCATE()
2969 if (Op0.getOpcode() == SPUISD::VEC2PREFSLOT && NodeVT == Op0VT) { in PerformDAGCombine()
3048 if (Op00.getOpcode() == SPUISD::VEC2PREFSLOT) { in PerformDAGCombine()
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DSPUNodes.td120 def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>;
DSPUISelDAGToDAG.cpp710 HandleSDNode Dummy(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT, in Select()
DSPUInstrInfo.td1425 // SPU::PREFSLOT2VEC and VEC2PREFSLOT re-interpretations of registers