Searched refs:VMRS (Results 1 – 24 of 24) sorted by relevance
| /external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
| D | vmrs.ll | 1 ; Test the "vmrs APSR_nzcv, FPSCR" form of the VMRS instruction.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | no-fpscr-liveness.ll | 14 ; VMRS instruction comes before any other instruction writing FPSCR:
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 194 #define VMRS 0xeef1fa10 macro
1594 return push_inst32(compiler, VMRS); in sljit_emit_fop1_cmp()
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| D | sljitNativeARM_32.c | 121 #define VMRS 0xeef1fa10 macro
1890 return push_inst(compiler, VMRS); in sljit_emit_fop1_cmp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 668 (instregex "VMRS")>;
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| D | ARMScheduleR52.td | 816 def : InstRW<[R52WriteNoRSRC_WRI], (instregex "VMRS")>;
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| D | ARMScheduleA57.td | 135 def : InstRW<[WriteNoop], (instregex "VMRS", "VMSR", "FMSTAT")>;
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| D | ARMInstrVFP.td | 2246 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
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| D | ARMISelDAGToDAG.cpp | 3966 .Case("fpscr", ARM::VMRS) in tryReadRegister()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 655 (instregex "VMRS")>;
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| D | ARMInstrVFP.td | 2078 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
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| D | ARMISelDAGToDAG.cpp | 4006 .Case("fpscr", ARM::VMRS) in tryReadRegister()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 1072 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 2350 3221798113U, // VMRS
5570 4U, // VMRS
8117 // VMRS
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| D | ARMGenMCCodeEmitter.inc | 1843 UINT64_C(250677776), // VMRS
8578 case ARM::VMRS:
13116 Feature_HasVFP2 | 0, // VMRS = 1830
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| D | ARMGenInstrInfo.inc | 1845 VMRS = 1830,
6525 …eEffects), 0x8c00ULL, ImplicitList12, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1830 = VMRS
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| D | ARMGenGlobalISel.inc | 19695 // (intrinsic_w_chain:{ *:[i32] } 981:{ *:[iPTR] }) => (VMRS:{ *:[i32] })
19696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMRS,
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| D | ARMGenDisassemblerTables.inc | 9941 /* 2797 */ MCD::OPC_Decode, 166, 14, 214, 2, // Opcode: VMRS
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| D | ARMGenAsmMatcher.inc | 10400 …{ 2144 /* vmrs */, ARM::VMRS, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_G…
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| D | ARMGenDAGISel.inc | 23124 /* 50540*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VMRS), 0|OPFL_Chain,
23127 // Dst: (VMRS:{ *:[i32] })
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| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 1391 2147518974U, // VMRS
4184 4U, // VMRS
7155 // VMRS
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| D | ARMGenInstrInfo.inc | 4568 …edSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1374 = VMRS
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| D | ARMGenDisassemblerTables.inc | 9151 /* 1462 */ MCD_OPC_Decode, 222, 10, 201, 2, // Opcode: VMRS
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 9088 if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) && in checkTargetMatchPredicate()
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