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Searched refs:VR128 (Results 1 – 25 of 56) sorted by relevance

123

/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrSSE.td123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
125 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
126 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
147 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
[all …]
DX86GenDAGISel.inc34 …// Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
35 // Dst: (VMOVNTPSmr addr:iPTR:$dst, VR128:v4f32:$src)
39 …// Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
40 // Dst: (VMOVNTDQmr addr:iPTR:$dst, VR128:v4f32:$src)
48 …// Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
49 // Dst: (MOVNTPSmr addr:iPTR:$dst, VR128:v4f32:$src)
56 …// Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
57 // Dst: (MOVNTDQmr addr:iPTR:$dst, VR128:v4f32:$src)
70 …// Src: (st VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
71 // Dst: (VMOVNTPDmr addr:iPTR:$dst, VR128:v2f64:$src)
[all …]
DX86InstrFMA.td19 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
20 (ins VR128:$src1, VR128:$src2),
23 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
24 (ins VR128:$src1, f128mem:$src2),
/external/llvm/lib/Target/X86/
DX86InstrXOP.td15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
17 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
46 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
49 [(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP;
54 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
56 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
[all …]
DX86InstrSSE.td333 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
[all …]
DX86InstrFMA.td43 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
44 (ins VR128:$src1, VR128:$src2, VR128:$src3),
47 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
48 VR128:$src1, VR128:$src3)))]>;
51 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
52 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
55 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
229 fma3s_int_forms<opc132, opc213, opc231, OpStr, "ss", VR128, ssmem>;
234 fma3s_int_forms<opc132, opc213, opc231, OpStr, "sd", VR128, sdmem>,
242 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrXOP.td15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
17 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[SchedWritePHAdd.XMM]>;
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP,
46 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
48 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
49 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
51 [(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP,
57 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
59 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
[all …]
DX86InstrSSE.td131 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
132 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
153 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
154 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
178 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
179 (ins VR128:$src1, VR128:$src2),
181 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))], d>,
186 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
187 (ins VR128:$src1, VR128:$src2),
220 VR128:$dst, VR128:$src1, VR128:$src2), 0>;
[all …]
DX86InstrVecCompiler.td21 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
22 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
23 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
24 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
25 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
27 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
28 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
29 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
30 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
[all …]
DX86InstrFMA.td106 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
108 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
110 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
312 VR128, ssmem, sched>;
318 VR128, sdmem, sched>, VEX_W;
335 def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector
337 (EltVT (extractelt (VT VR128:$src1), (iPTR 0))),
340 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)),
341 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;
343 def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector
[all …]
DX86InstrMMX.td245 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
248 (i64 (extractelt (v2i64 VR128:$src),
251 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
253 [(set VR128:$dst,
509 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
512 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
515 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
518 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
521 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
525 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td45 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),
46 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>;
153 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
154 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
155 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
156 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
201 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
203 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
204 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
206 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
[all …]
DSystemZRegisterInfo.td219 class VR128<bits<16> num, string n, FPR64 high>
227 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
253 defm VR128 : SystemZRegClass<"VR128",
269 def v128b : TypedReg<v16i8, VR128>;
270 def v128h : TypedReg<v8i16, VR128>;
271 def v128f : TypedReg<v4i32, VR128>;
272 def v128g : TypedReg<v2i64, VR128>;
273 def v128q : TypedReg<v16i8, VR128>;
274 def v128eb : TypedReg<v4f32, VR128>;
275 def v128db : TypedReg<v2f64, VR128>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DTargetInstrSpec.td4 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
5 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
7 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
8 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
64 def VR128 : RegisterClass<[v2i64, v2f64],
78 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
83 !subst(REGCLASS, VR128, operand))))>;
85 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
90 !subst(REGCLASS, VR128, operand))))>;
Dcast.td63 def VR128 : RegisterClass<[v2i64, v2f64],
73 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
75 … [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_ps")) VR128:$src1, VR128:$src2))]>;
77 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
79 … [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_pd")) VR128:$src1, VR128:$src2))]>;
85 Inst<opcode,(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
87 [(set VR128:$dst, (Intr VR128:$src1, VR128:$src2))]>;
DMultiPat.td67 def VR128 : RegisterClass<[v2i64, v2f64],
90 !subst(REGCLASS, VR128,
95 !subst(REGCLASS, VR128,
99 def PS : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
102 def PD : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
112 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
113 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
/external/llvm/test/TableGen/
DTargetInstrSpec.td4 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
5 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
7 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
8 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
64 def VR128 : RegisterClass<[v2i64, v2f64],
86 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
91 !subst(REGCLASS, VR128, Decls.operand))))>;
93 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
98 !subst(REGCLASS, VR128, Decls.operand))))>;
Dcast.td63 def VR128 : RegisterClass<[v2i64, v2f64],
73 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
75 … [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_ps")) VR128:$src1, VR128:$src2))]>;
77 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
79 … [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_pd")) VR128:$src1, VR128:$src2))]>;
85 Inst<opcode,(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
87 [(set VR128:$dst, (Intr VR128:$src1, VR128:$src2))]>;
DMultiPat.td67 def VR128 : RegisterClass<[v2i64, v2f64],
98 !subst(REGCLASS, VR128,
103 !subst(REGCLASS, VR128,
107 def PS : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
110 def PD : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
120 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
121 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td47 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),
48 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>;
169 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
170 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
171 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
172 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
224 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
226 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
227 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
229 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
[all …]
DSystemZRegisterInfo.td231 class VR128<bits<16> num, string n, FPR64 high>
239 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
265 defm VR128 : SystemZRegClass<"VR128",
282 def v128b : TypedReg<v16i8, VR128>;
283 def v128h : TypedReg<v8i16, VR128>;
284 def v128f : TypedReg<v4i32, VR128>;
285 def v128g : TypedReg<v2i64, VR128>;
286 def v128q : TypedReg<v16i8, VR128>;
287 def v128sb : TypedReg<v4f32, VR128>;
288 def v128db : TypedReg<v2f64, VR128>;
[all …]
/external/swiftshader/third_party/LLVM/test/TableGen/
Dcast.td58 def VR128 : RegisterClass<[v2i64, v2f64],
68 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
70 … [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_ps")) VR128:$src1, VR128:$src2))]>;
72 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
74 … [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_pd")) VR128:$src1, VR128:$src2))]>;
80 Inst<opcode,(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
82 [(set VR128:$dst, (Intr VR128:$src1, VR128:$src2))]>;
DTargetInstrSpec.td1 // RUN: llvm-tblgen %s | grep {\\\[(set VR128:\$dst, (int_x86_sse2_add_pd VR128:\$src1, VR128:\$src…
2 // RUN: llvm-tblgen %s | grep {\\\[(set VR128:\$dst, (int_x86_sse2_add_ps VR128:\$src1, VR128:\$src…
59 def VR128 : RegisterClass<[v2i64, v2f64],
81 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
86 !subst(REGCLASS, VR128, Decls.operand))))>;
88 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
93 !subst(REGCLASS, VR128, Decls.operand))))>;
DMultiPat.td67 def VR128 : RegisterClass<[v2i64, v2f64],
98 !subst(REGCLASS, VR128,
103 !subst(REGCLASS, VR128,
107 def PS : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
110 def PD : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
120 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
121 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc1185 …(add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPADDQrr:{ *:[v2i64…
1196 …(add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PADDQrr:{ *:[v2i64]…
1231 …VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2), VR128:{ *:[v4i32] }:$src3) => (VPMACSDDrr…
1253 …VR128:{ *:[v4i32] }:$src3, (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2…
1269 …(add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPADDDrr:{ *:[v4i32…
1280 …(add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PADDDrr:{ *:[v4i32]…
1344 …VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2), VR128:{ *:[v8i16] }:$src3) => (VPMACSWWrr…
1366 …VR128:{ *:[v8i16] }:$src3, (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2…
1382 …(add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPADDWrr:{ *:[v8i16…
1393 …(add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PADDWrr:{ *:[v8i16]…
[all …]

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