| /external/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| D | fd4_program.c | 141 VS = 0, enumerator
154 s[VS].v = fd4_emit_get_vp(emit); in setup_stages()
184 if ((s[VS].instrlen + s[FS].instrlen) > 64) { in setup_stages()
188 s[VS].instrlen = 0; in setup_stages()
189 } else if (s[VS].instrlen < 64) { in setup_stages()
194 s[VS].instrlen = 0; in setup_stages()
198 s[VS].constlen = 66; in setup_stages()
199 s[FS].constlen = 128 - s[VS].constlen; in setup_stages()
200 s[VS].instroff = 0; in setup_stages()
201 s[VS].constoff = 0; in setup_stages()
[all …]
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| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | fd5_program.c | 257 VS = 0, enumerator
270 s[VS].v = fd5_emit_get_vp(emit); in setup_stages()
300 if ((s[VS].instrlen + s[FS].instrlen) > 64) { in setup_stages()
304 s[VS].instrlen = 0; in setup_stages()
305 } else if (s[VS].instrlen < 64) { in setup_stages()
310 s[VS].instrlen = 0; in setup_stages()
321 s[VS].instroff = 0; in setup_stages()
342 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS); in fd5_program_emit()
343 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ); in fd5_program_emit()
344 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE); in fd5_program_emit()
[all …]
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| /external/harfbuzz_ng/src/ |
| D | hb-ot-shape-complex-use-machine.rl | 66 VS = 21; # VARIATION_SELECTOR
96 consonant_modifiers = CMAbv* CMBlw* ((ZWJ?.h.ZWJ? B | SUB) VS? CMAbv? CMBlw*)*;
112 (R|CS)? (B | GB) VS?
117 (R|CS)? (B | GB) VS?
125 number_joiner_terminated_cluster = N VS? (HN N VS?)* HN;
126 numeral_cluster = N VS? (HN N VS?)*;
127 symbol_cluster = S VS? SMAbv* SMBlw*;
128 independent_cluster = (IND | O | Rsv | WJ) VS?;
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| D | hb-ot-shape-complex-myanmar-machine.rl | 60 VS = 30;
73 main_vowel_group = (VPre.VS?)* VAbv* VBlw* A* (DB As?)?;
80 consonant_syllable = (k|CS)? (c|IV|D|GB).VS? (H (c|IV).VS?)* syllable_tail;
82 broken_cluster = k? VS? syllable_tail;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Utils/ |
| D | ARMBaseInfo.h | 38 VS, // Overflow Unordered enumerator
58 case VS: return VC; in getOppositeCondition()
59 case VC: return VS; in getOppositeCondition()
78 case ARMCC::VS: return "vs"; in ARMCondCodeToString()
101 .Case("vs", ARMCC::VS) in ARMCondCodeFromString()
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| /external/libdrm/intel/tests/ |
| D | gm45-3d.batch-ref.txt | 14 0x12300034: 0x00007e20: VS binding table
31 0x12300078: 0x00007d60: VS state
63 0x123000f8: 0x00007b40: VS binding table
69 0x12300110: 0x00007aa0: VS state
92 0x1230016c: 0x00007aa0: VS state
110 0x123001b4: 0x00007aa0: VS state
128 0x123001fc: 0x00007aa0: VS state
146 0x12300244: 0x00007aa0: VS state
158 0x12300274: 0x000079a0: VS state
186 0x123002e4: 0x000079a0: VS state
[all …]
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| D | gen4-3d.batch-ref.txt | 14 0x12300034: 0x00007e20: VS binding table
30 0x12300074: 0x00007d60: VS state
62 0x123000f4: 0x00007b40: VS binding table
68 0x1230010c: 0x00007aa0: VS state
91 0x12300168: 0x00007aa0: VS state
109 0x123001b0: 0x00007aa0: VS state
127 0x123001f8: 0x00007aa0: VS state
145 0x12300240: 0x00007aa0: VS state
157 0x12300270: 0x000079a0: VS state
185 0x123002e0: 0x000079a0: VS state
[all …]
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| D | gen5-3d.batch-ref.txt | 16 0x1230003c: 0x00007e20: VS binding table
34 0x12300084: 0x00007d60: VS state
66 0x12300104: 0x00007b40: VS binding table
73 0x12300120: 0x00007aa0: VS state
99 0x12300188: 0x00007aa0: VS state
118 0x123001d4: 0x00007aa0: VS state
137 0x12300220: 0x00007aa0: VS state
158 0x12300274: 0x00007aa0: VS state
171 0x123002a8: 0x000079a0: VS state
200 0x1230031c: 0x000079a0: VS state
[all …]
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| D | gen6-3d.batch-ref.txt | 49 0x123000c0: 0x00000100: VS entries 256, alloc size 1 (1024bit row)
55 0x123000d8: 0x78021302: 3DSTATE_SAMPLER_STATE_POINTERS: VS mod 1, GS mod 1, PS mod 1
56 0x123000dc: 0x00000000: VS sampler state
69 0x12300110: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable
126 0x123001f4: 0x78011302: 3DSTATE_BINDING_TABLE_POINTERS: VS mod 1, GS mod 1, PS mod 1
127 0x123001f8: 0x00007d40: VS binding table
180 0x123002cc: 0x00000100: VS entries 256, alloc size 1 (1024bit row)
196 0x1230030c: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable
247 0x123003d8: 0x78011302: 3DSTATE_BINDING_TABLE_POINTERS: VS mod 1, GS mod 1, PS mod 1
248 0x123003dc: 0x00007a00: VS binding table
[all …]
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_urb.c | 39 #define VS 0 macro
124 if (vsize < limits[VS].min_entry_size) in brw_calculate_urb_fence()
125 vsize = limits[VS].min_entry_size; in brw_calculate_urb_fence()
142 brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; in brw_calculate_urb_fence()
157 brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; in brw_calculate_urb_fence()
166 brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; in brw_calculate_urb_fence()
171 brw->urb.nr_vs_entries = limits[VS].min_nr_entries; in brw_calculate_urb_fence()
|
| /external/deqp/framework/referencerenderer/ |
| D | design.txt | 30 + VS generic output count
32 + VS execution queue
35 + run VS for all vertices at once
60 + position & point size from VS
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | fma-combine.ll | 391 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], 1.0, [[VX:v[0-9]]]
392 ; SI-NOFMA: v_mul_f32_e32 {{v[0-9]}}, [[VS]], [[VY:v[0-9]]]
407 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], 1.0, [[VX:v[0-9]]]
408 ; SI-NOFMA: v_mul_f32_e32 {{v[0-9]}}, [[VY:v[0-9]]], [[VS]]
423 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], -1.0, [[VX:v[0-9]]]
424 ; SI-NOFMA: v_mul_f32_e32 {{v[0-9]}}, [[VS]], [[VY:v[0-9]]]
439 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], -1.0, [[VX:v[0-9]]]
440 ; SI-NOFMA: v_mul_f32_e32 {{v[0-9]}}, [[VY:v[0-9]]], [[VS]]
455 ; SI-NOFMA: v_sub_f32_e32 [[VS:v[0-9]]], 1.0, [[VX:v[0-9]]]
456 ; SI-NOFMA: v_mul_f32_e32 {{v[0-9]}}, [[VS]], [[VY:v[0-9]]]
[all …]
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 36 VS, // Overflow Unordered enumerator
56 case VS: return VC; in getOppositeCondition()
57 case VC: return VS; in getOppositeCondition()
76 case ARMCC::VS: return "vs"; in ARMCondCodeToString()
|
| /external/u-boot/arch/arm/dts/ |
| D | sun5i-a13-inet-86vs.dts | 5 * Minimal dts file for the iNet 86VS for u-boot only
12 model = "iNet 86VS";
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/vscode/tablegen/ |
| D | vsc-extension-quickstart.md | 1 # Welcome to your VS Code Extension
19 * you can also reload (`Ctrl+R` or `Cmd+R` on Mac) the VS Code window with your extension to load y…
22 * To add features such as intellisense, hovers and validators check out the VS Code extenders docum…
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 36 VS, // Overflow Unordered enumerator
56 case VS: return VC; in getOppositeCondition()
57 case VC: return VS; in getOppositeCondition()
77 case ARMCC::VS: return "vs"; in ARMCondCodeToString()
|
| /external/Reactive-Extensions/RxCpp/ |
| D | .gitattributes | 19 # are conflicts (Merging from VS is not affected by the settings below, in VS
21 # file extensions to fail to load in VS. An alternative would be to treat
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | inst-select-ashr.mir | 51 ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[CS]], [[VGPR0]]
55 ; SI: [[SV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[CS]], [[VS]]
56 ; VI: [[SV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VS]], [[CS]]
|
| D | inst-select-or.mir | 31 ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VGPR0]]
35 ; GCN: [[SV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VS]]
|
| /external/deqp-deps/SPIRV-Tools/kokoro/scripts/windows/ |
| D | build.bat | 38 echo "Using VS 2017..."
41 echo "Using VS 2015..."
44 echo "Using VS 2013..."
|
| /external/swiftshader/third_party/SPIRV-Tools/kokoro/scripts/windows/ |
| D | build.bat | 38 echo "Using VS 2017..."
41 echo "Using VS 2015..."
44 echo "Using VS 2013..."
|
| /external/clang/test/SemaCXX/ |
| D | warn-unused-filescoped.cpp | 71 struct VS { struct
75 struct SVS : public VS {
|
| /external/python/cpython3/Modules/_decimal/libmpdec/ |
| D | README.txt | 33 vcstdint.h -> stdint.h (included in VS 2010 but not in VS 2008).
34 vcdiv64.asm -> Double word division used in typearith.h. VS 2008 does
|
| /external/expat/win32/ |
| D | README.txt | 11 project directories. This solution file can be opened in VS 2015 or VS 2017
12 and should be upgraded automatically if VS 2013 is not also installed.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonDepIICHVX.td | 152 InstrItinData <tc_41f4b64e, /*SLOT0123,VS*/
162 InstrItinData <tc_45453b98, /*SLOT0123,VS*/
282 InstrItinData <tc_7fa8b40f, /*SLOT0123,VS*/
341 InstrItinData <tc_9b9642a1, /*SLOT0123,VS*/
406 InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/
426 InstrItinData <tc_d2cb81ea, /*SLOT0123,VS*/
593 InstrItinData <tc_41f4b64e, /*SLOT0123,VS*/
603 InstrItinData <tc_45453b98, /*SLOT0123,VS*/
723 InstrItinData <tc_7fa8b40f, /*SLOT0123,VS*/
782 InstrItinData <tc_9b9642a1, /*SLOT0123,VS*/
[all …]
|