| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | IRTranslator.cpp | 38 unsigned &ValReg = ValToVReg[&Val]; in getOrCreateVReg() local
40 if (!ValReg) { in getOrCreateVReg()
48 ValReg = VReg; in getOrCreateVReg()
51 return ValReg; in getOrCreateVReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 156 unsigned CallLowering::ValueHandler::extendRegister(unsigned ValReg, in extendRegister() argument
165 return ValReg; in extendRegister()
168 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
173 MIRBuilder.buildSExt(NewReg, ValReg); in extendRegister()
178 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86SelectionDAGInfo.cpp | 86 unsigned ValReg; in EmitTargetCodeForMemset() local
93 ValReg = X86::AX; in EmitTargetCodeForMemset()
98 ValReg = X86::EAX; in EmitTargetCodeForMemset()
103 ValReg = X86::RAX; in EmitTargetCodeForMemset()
109 ValReg = X86::AL; in EmitTargetCodeForMemset()
120 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), in EmitTargetCodeForMemset()
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| D | X86FastISel.cpp | 300 unsigned ValReg = getRegForValue(Val); in X86FastEmitStore() local
301 if (ValReg == 0) in X86FastEmitStore()
304 return X86FastEmitStore(VT, ValReg, AM); in X86FastEmitStore()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86SelectionDAGInfo.cpp | 129 unsigned ValReg; in EmitTargetCodeForMemset() local
136 ValReg = X86::AX; in EmitTargetCodeForMemset()
141 ValReg = X86::EAX; in EmitTargetCodeForMemset()
146 ValReg = X86::RAX; in EmitTargetCodeForMemset()
152 ValReg = X86::AL; in EmitTargetCodeForMemset()
163 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
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| D | X86FastISel.cpp | 93 bool X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
496 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore() argument
517 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1); in X86FastEmitStore()
518 ValReg = AndResult; in X86FastEmitStore()
660 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
663 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill)); in X86FastEmitStore()
707 unsigned ValReg = getRegForValue(Val); in X86FastEmitStore() local
708 if (ValReg == 0) in X86FastEmitStore()
712 return X86FastEmitStore(VT, ValReg, ValKill, AM, MMO, Aligned); in X86FastEmitStore()
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| /external/llvm/lib/Target/X86/ |
| D | X86SelectionDAGInfo.cpp | 109 unsigned ValReg; in EmitTargetCodeForMemset() local
116 ValReg = X86::AX; in EmitTargetCodeForMemset()
121 ValReg = X86::EAX; in EmitTargetCodeForMemset()
126 ValReg = X86::RAX; in EmitTargetCodeForMemset()
132 ValReg = X86::AL; in EmitTargetCodeForMemset()
143 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
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| D | X86FastISel.cpp | 93 bool X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
501 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore() argument
519 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1); in X86FastEmitStore()
520 ValReg = AndResult; in X86FastEmitStore()
639 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
642 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill)); in X86FastEmitStore()
684 unsigned ValReg = getRegForValue(Val); in X86FastEmitStore() local
685 if (ValReg == 0) in X86FastEmitStore()
689 return X86FastEmitStore(VT, ValReg, ValKill, AM, MMO, Aligned); in X86FastEmitStore()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 100 unsigned extendRegister(unsigned ValReg, CCValAssign &VA);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1751 unsigned ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1755 .addReg(ValReg) in EmitInstruction()
1762 .addReg(ValReg) in EmitInstruction()
1765 .addReg(ValReg) in EmitInstruction()
1772 .addReg(ValReg) in EmitInstruction()
1817 unsigned ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1821 .addReg(ValReg) in EmitInstruction()
1831 .addReg(ValReg) in EmitInstruction()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1730 unsigned ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1734 .addReg(ValReg) in EmitInstruction()
1741 .addReg(ValReg) in EmitInstruction()
1744 .addReg(ValReg) in EmitInstruction()
1751 .addReg(ValReg) in EmitInstruction()
1796 unsigned ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1800 .addReg(ValReg) in EmitInstruction()
1810 .addReg(ValReg) in EmitInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1655 unsigned ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1660 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); in EmitInstruction()
1671 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); in EmitInstruction()
1674 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); in EmitInstruction()
1684 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); in EmitInstruction()
1739 unsigned ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1744 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); in EmitInstruction()
1758 TmpInst.addOperand(MCOperand::CreateReg(ValReg)); in EmitInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 1029 const unsigned ValReg = I.getOperand(0).getReg(); in select() local
1030 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
1065 if (auto CVal = getConstantVRegVal(ValReg, MRI)) { in select()
|