Searched refs:WR_ACCESS_OFFSET (Results 1 – 2 of 2) sorted by relevance
| /external/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| D | clk-core.c | 21 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */ macro
92 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in peri_clk_enable()
154 writel(0, base + WR_ACCESS_OFFSET); in peri_clk_enable()
268 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
313 writel(0, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
344 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in bus_clk_enable()
368 writel(0, base + WR_ACCESS_OFFSET); in bus_clk_enable()
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| /external/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| D | clk-core.c | 21 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */ macro
92 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in peri_clk_enable()
154 writel(0, base + WR_ACCESS_OFFSET); in peri_clk_enable()
268 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
313 writel(0, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
344 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in bus_clk_enable()
368 writel(0, base + WR_ACCESS_OFFSET); in bus_clk_enable()
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