| /external/libxaac/decoder/armv8/ |
| D | ixheaacd_no_lap1.s | 56 LSL X7, X3, #1
76 ST1 {V27.H}[2], [X1], X7
79 ST1 {V27.H}[3], [X1], X7
81 ST1 {V27.H}[0], [X1], X7
83 ST1 {V27.H}[1], [X1], X7
91 ST1 {V27.H}[2], [X1], X7
94 ST1 {V27.H}[3], [X1], X7
96 ST1 {V27.H}[0], [X1], X7
98 ST1 {V27.H}[1], [X1], X7
106 ST1 {V27.H}[2], [X1], X7
[all …]
|
| D | ixheaacd_overlap_add2.s | 57 ADD X7, X1, X12
61 SUB X7, X7, #12
68 LD2 {V6.4H, V7.4H}, [X7], X12
85 LD2 {V14.4H, V15.4H}, [X7], X12
99 LD2 {V6.4H, V7.4H}, [X7], X12
120 LD2 {V14.4H, V15.4H}, [X7], X12
163 LSL X7, X7, #2
166 ADD X7, X7, X9
247 ST1 {V24.S}[0], [X7], X8
249 ST1 {V24.S}[1], [X7], X8
[all …]
|
| D | ixheaacd_sbr_imdct_using_fft.s | 62 MOV X4, X7
80 MOV X7 , X2
128 ADD X7, X7, X12, LSL #3
129 LD2 {V0.S, V1.S}[2], [X7] , X1
130 ADD X7, X7, X1
131 LD2 {V4.S, V5.S}[2], [X7] , X1
132 SUB X7, X7, X1, LSL #1
143 LD2 {V2.S, V3.S}[2], [X7] , X1
144 ADD X7, X7, X1
148 LD2 {V6.S, V7.S}[2], [X7], X1
[all …]
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| D | ixheaacd_imdct_using_fft.s | 65 ADD X7, X0, X29
98 MOv X4, X7
110 MOv X7 , X2
158 ADD X7, X7, X12, LSL #3
159 LD2 {v0.S, v1.S}[2], [X7] , X1
160 ADD X7, X7, X1
161 LD2 {v4.S, v5.S}[2], [X7] , X1
162 SUB X7, X7, X1, LSL #1
173 LD2 {v2.S, v3.S}[2], [X7] , X1
174 ADD X7, X7, X1
[all …]
|
| /external/clang/test/CXX/except/except.spec/ |
| D | p14-ir.cpp | 50 struct X7 { struct
51 X7();
55 struct X9 : X6, X7 { };
|
| /external/clang/test/CodeGen/ |
| D | override-layout.c | 68 struct X7 { struct
73 void use_X7() { struct X7 x7; x7.y = x7.x = sizeof(struct X7); } in use_X7() argument
77 struct X7 x;
|
| /external/clang/test/SemaTemplate/ |
| D | temp_explicit.cpp | 131 template<typename T> struct X7 { }; // expected-note{{here}} struct
137 template struct X7<int>; variable
148 template struct X7<double>; // expected-warning{{must occur in namespace}} variable
|
| D | instantiate-expr-1.cpp | 149 typedef X<7> X7; typedef
151 void f() { X7(); } // expected-note{{instantiation}} in f()
|
| D | instantiate-function-1.cpp | 86 template <typename T> struct X7 { struct
92 template struct X7<int>; argument
|
| /external/deqp-deps/glslang/Test/ |
| D | preprocessor.function_macro.vert | 8 #define REALLY_LONG_MACRO_NAME_WITH_MANY_PARAMETERS(X1, X2, X3, X4, X5, X6, X7,\
9 X8, X9, X10, X11, X12) X1+X2+X3+X4+X5+X6+X7+X8+X9+X10+X11+X12
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.td | 57 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
58 // i128 is split to two i64s, we can't fit half to register X7.
63 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
65 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
102 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
103 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
146 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
147 // i128 is split to two i64s, we can't fit half to register X7.
152 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
154 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
[all …]
|
| /external/boringssl/src/crypto/fipsmodule/md4/ |
| D | md4.c | 139 uint32_t X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15; in md4_block_data_order() local
169 X7 = l; in md4_block_data_order()
173 R0(B, C, D, A, X7, 19, 0); in md4_block_data_order()
210 R1(D, A, B, C, X7, 5, 0x5A827999L); in md4_block_data_order()
228 R2(C, D, A, B, X7, 11, 0x6ED9EBA1L); in md4_block_data_order()
|
| /external/clang/test/CXX/expr/expr.unary/expr.new/ |
| D | p20.cpp | 130 struct X7 {
138 new X7<1>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.td | 61 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
62 // i128 is split to two i64s, we can't fit half to register X7.
67 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
69 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
108 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
109 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
160 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
161 // i128 is split to two i64s, we can't fit half to register X7.
166 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
168 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/ToolDrivers/llvm-dlltool/ |
| D | DlltoolDriver.cpp | 43 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ argument
45 X9, X8, OPT_##GROUP, OPT_##ALIAS, X7, X12},
|
| /external/llvm/lib/LibDriver/ |
| D | LibDriver.cpp | 43 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X6, X7, X8, X9, X10) \ argument
45 X1, X2, X9, X10, OPT_##ID, llvm::opt::Option::KIND##Class, X8, X7, \
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/ToolDrivers/llvm-lib/ |
| D | LibDriver.cpp | 44 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ argument
46 X9, X8, OPT_##GROUP, OPT_##ALIAS, X7, X12},
|
| /external/clang/test/SemaCXX/ |
| D | new-delete.cpp | 188 class X7 { class
193 class X8 : public X6, public X7 {
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenCallingConv.inc | 140 …ch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
166 AArch64::X7
176 …ch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
384 …ch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
410 AArch64::X7
420 …ch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
860 …ch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
870 …ch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
969 …ch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
979 …ch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | armv8.4a-ldst-error.s | 52 LDAPURSW X7, [X0, #256]
|
| D | armv8.4a-ldst.s | 115 LDAPURSW X7, [X0, #255]
|
| /external/webrtc/data/voice_engine/stereo_rtp_files/ |
| D | toggling_stereo_g729_pt18_pt125.rtp | 113 … ��������εI��X���\w�p{z� ���������I��X)���I��� ���������UI��X7 � �qe�K� ������…
119 …������I��X�k�pD� ���������EI��X����֢ps�� �������ߕI��Xy��}�CqLǑ� ���������I��X7
126 �I��X�i��X� N��i��X� N��(� �� �}I�� I��X���cp�L��H���cp�L��H�(� �� "�}J�� UI��X7�������7�����…
300 %[S� ���Y�(���I��X7
338 …$�] �=ht$�] ��(� ��k�}���j�I��Xhc��Wu� -hc��Wu� -�(� ��k�}���j�I��X7(�M�J�J�7(�M�J�J��(� …
340 …%U�� �=b2�%U�� ��(� ��l�}���rUI��X42r���~f42r���~f�(� ��l �}���r�I��X72�T�V�&g72�T�V�&g�(…
420 …X7*m=�5�Jw7*m=�5�Jw�(� ���܀}����%I��X<���\�rNt�<���\�rNt��(� ����}����uI��X7�����n̛7�����n̛�…
457 …��2֧�(� ���n�} ����I��X�4t��������4t��������(� ���x�} ���I��X7�`ĸ�d��7�`ĸ�d���(� �����} ���…
470 ��(%I��X Bg��R�V� Bg��R�V��(� ���ƀ} ��(uI��X8���2B�6X8���2B�6X�(� ���Ѐ} ��(�I��X7"#�*;"�}7"#…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopStrengthReduce/X86/ |
| D | lsr-insns-1.ll | 28 ; INSN-NEXT: [[X7:%.*]] = bitcast i32* [[X:%.*]] to i8*
34 ; INSN-NEXT: [[UGLYGEP8:%.*]] = getelementptr i8, i8* [[X7]], i64 [[LSR_IV]]
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 38 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; in getPPCRegisterNumbering()
|
| /external/clang/test/Parser/ |
| D | missing-end-4.m | 18 @interface X7 // expected-error {{missing '@end'}}
|