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Searched refs:X86_MC (Results 1 – 15 of 15) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp45 std::string X86_MC::ParseX86Triple(StringRef TT) { in ParseX86Triple()
61 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, in GetCpuIDAndInfo()
114 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family, in DetectFamilyModel()
127 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) { in getDwarfRegFlavour()
143 unsigned X86_MC::getX86RegNum(unsigned RegNo) { in getX86RegNum()
232 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { in InitLLVM2SEHRegisterMapping()
235 int SEH = X86_MC::getX86RegNum(Reg); in InitLLVM2SEHRegisterMapping()
256 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, in createX86MCSubtargetInfo()
258 std::string ArchFS = X86_MC::ParseX86Triple(TT); in createX86MCSubtargetInfo()
294 X86_MC::getDwarfRegFlavour(TT, false), in createX86MCRegisterInfo()
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DX86MCTargetDesc.h50 namespace X86_MC {
DX86MCCodeEmitter.cpp50 return X86_MC::getX86RegNum(MO.getReg()); in GetX86RegNum()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86Subtarget.cpp185 if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) in AutoDetectSubtargetFeatures()
188 X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); in AutoDetectSubtargetFeatures()
242 X86_MC::DetectFamilyModel(EAX, Family, Model); in AutoDetectSubtargetFeatures()
253 X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in AutoDetectSubtargetFeatures()
DX86CodeEmitter.cpp356 MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg))); in emitRegModRMByte()
494 BaseRegNo = X86_MC::getX86RegNum(BaseReg); in emitMemModRMByte()
570 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg()); in emitMemModRMByte()
575 unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg); in emitMemModRMByte()
578 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg()); in emitMemModRMByte()
821 X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg())); in emitInstruction()
856 X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg())); in emitInstruction()
866 X86_MC::getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands) in emitInstruction()
878 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg())); in emitInstruction()
893 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj); in emitInstruction()
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DX86RegisterInfo.cpp57 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false), in X86RegisterInfo()
58 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)), in X86RegisterInfo()
60 X86_MC::InitLLVM2SEHRegisterMapping(this); in X86RegisterInfo()
95 int reg = X86_MC::getX86RegNum(i); in getSEHRegNum()
DX86ISelLowering.cpp9513 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); in LowerINIT_TRAMPOLINE()
9514 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); in LowerINIT_TRAMPOLINE()
9616 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); in LowerINIT_TRAMPOLINE()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp44 std::string X86_MC::ParseX86Triple(const Triple &TT) { in ParseX86Triple()
56 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { in getDwarfRegFlavour()
68 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { in initLLVMToSEHAndCVRegMapping()
123 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, in createX86MCSubtargetInfo()
125 std::string ArchFS = X86_MC::ParseX86Triple(TT); in createX86MCSubtargetInfo()
152 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), in createX86MCRegisterInfo()
153 X86_MC::getDwarfRegFlavour(TT, true), RA); in createX86MCRegisterInfo()
154 X86_MC::initLLVMToSEHAndCVRegMapping(X); in createX86MCRegisterInfo()
252 X86_MC::createX86MCSubtargetInfo); in LLVMInitializeX86TargetMC()
DX86MCTargetDesc.h54 namespace X86_MC {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp48 std::string X86_MC::ParseX86Triple(const Triple &TT) { in ParseX86Triple()
60 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { in getDwarfRegFlavour()
72 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { in initLLVMToSEHAndCVRegMapping()
203 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, in createX86MCSubtargetInfo()
205 std::string ArchFS = X86_MC::ParseX86Triple(TT); in createX86MCSubtargetInfo()
232 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), in createX86MCRegisterInfo()
233 X86_MC::getDwarfRegFlavour(TT, true), RA); in createX86MCRegisterInfo()
234 X86_MC::initLLVMToSEHAndCVRegMapping(X); in createX86MCRegisterInfo()
300 namespace X86_MC { namespace
445 return new X86_MC::X86MCInstrAnalysis(Info); in createX86MCInstrAnalysis()
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DX86MCTargetDesc.h57 namespace X86_MC {
/external/llvm/lib/Target/X86/
DX86RegisterInfo.cpp52 X86_MC::getDwarfRegFlavour(TT, false), in X86RegisterInfo()
53 X86_MC::getDwarfRegFlavour(TT, true), in X86RegisterInfo()
55 X86_MC::initLLVMToSEHAndCVRegMapping(this); in X86RegisterInfo()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.cpp47 X86_MC::getDwarfRegFlavour(TT, false), in X86RegisterInfo()
48 X86_MC::getDwarfRegFlavour(TT, true), in X86RegisterInfo()
50 X86_MC::initLLVMToSEHAndCVRegMapping(this); in X86RegisterInfo()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenSubtargetInfo.inc16527 namespace X86_MC {
16606 X86_MC::isThreeOperandsLEA(*MI)
16637 } // end of namespace X86_MC
16653 return X86_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
16814 namespace X86_MC {
16958 return X86_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
DX86GenInstrInfo.inc50162 namespace X86_MC {
50166 } // end X86_MC namespace
50175 namespace X86_MC {
50199 } // end X86_MC namespace