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Searched refs:XCHAL_HAVE_XLT_CACHEATTR (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/xtensa/include/asm/arch-dc232b/
Dcore.h406 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/external/u-boot/arch/xtensa/include/asm/arch-dc233c/
Dcore.h437 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/external/u-boot/arch/xtensa/include/asm/arch-de212/
Dcore.h558 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro