Searched refs:XER (Results 1 – 18 of 18) sorted by relevance
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 230 def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 232 // Carry bit. In the architecture this is really bit 0 of the XER register 236 let Aliases = [XER]; 385 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
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D | README_P9.txt | 587 Move to CR from XER Extended (mcrxrx):
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/external/python/pyasn1/ |
D | TODO.rst | 13 * XER
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/external/u-boot/include/ |
D | ppc_asm.tmpl | 180 mfspr r20,XER; \
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/external/u-boot/arch/powerpc/cpu/mpc8xx/ |
D | start.S | 304 mtspr XER,r2
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/external/libunwind/src/ptrace/ |
D | _UPT_reg_offset.c | 386 [UNW_PPC##b##_XER] = UNW_PPC_PT(XER), \
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/external/scapy/scapy/asn1/ |
D | asn1.py | 92 XER = 9 variable in ASN1_Codecs
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 261 // Carry bit. In the architecture this is really bit 0 of the XER register
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/external/u-boot/arch/powerpc/include/asm/ |
D | processor.h | 690 #define XER SPRN_XER macro
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/external/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 216 // Carry bit. In the architecture this is really bit 0 of the XER register
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D | p9-instrs.txt | 158 // Move to CR from XER Extended X-form p119
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D | README_P9.txt | 587 Move to CR from XER Extended (mcrxrx):
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/external/u-boot/arch/powerpc/cpu/mpc86xx/ |
D | start.S | 527 mtspr XER,r2
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/external/u-boot/doc/ |
D | README.POST | 427 loading a fixed value into the XER register (mtspr), moving XER
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/external/u-boot/arch/powerpc/cpu/mpc83xx/ |
D | start.S | 463 mtspr XER,r2
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/external/u-boot/arch/powerpc/cpu/mpc85xx/ |
D | start.S | 1328 mtspr XER,r2
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/external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
D | 2013-1_UNLOCODE_CodeListPart3.csv | 12723 ,"US","XER","Cleona","Cleona","PA","--3-----","RQ","9307",,,
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D | 2013-1_UNLOCODE_CodeListPart1.csv | 40079 ,"FR","XER","Port-Sainte-Marie","Port-Sainte-Marie","41","1----6--","RQ","1101",,,""
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