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Searched refs:activate_0_and_1_wait1 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dwrap_sdram_config.c191 .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dsdram_gen5.h125 u8 activate_0_and_1_wait1; member
/external/u-boot/drivers/ddr/altera/
Dsequencer.c3152 writel(rwcfg->activate_0_and_1_wait1, in mem_precharge_and_activate()