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Searched refs:anatop (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/arch/arm/dts/
Dimx6sl.dtsi512 anatop: anatop@020c8000 { label
513 compatible = "fsl,imx6sl-anatop",
514 "fsl,imx6q-anatop",
522 compatible = "fsl,anatop-regulator";
527 anatop-reg-offset = <0x110>;
528 anatop-vol-bit-shift = <8>;
529 anatop-vol-bit-width = <5>;
530 anatop-min-bit-val = <4>;
531 anatop-min-voltage = <800000>;
532 anatop-max-voltage = <1375000>;
[all …]
Dimx6sx.dtsi559 anatop: anatop@020c8000 { label
560 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
568 compatible = "fsl,anatop-regulator";
573 anatop-reg-offset = <0x110>;
574 anatop-vol-bit-shift = <8>;
575 anatop-vol-bit-width = <5>;
576 anatop-min-bit-val = <4>;
577 anatop-min-voltage = <800000>;
578 anatop-max-voltage = <1375000>;
582 compatible = "fsl,anatop-regulator";
[all …]
Dimx6qdl.dtsi618 anatop: anatop@020c8000 { label
619 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
626 compatible = "fsl,anatop-regulator";
631 anatop-reg-offset = <0x110>;
632 anatop-vol-bit-shift = <8>;
633 anatop-vol-bit-width = <5>;
634 anatop-min-bit-val = <4>;
635 anatop-min-voltage = <800000>;
636 anatop-max-voltage = <1375000>;
640 compatible = "fsl,anatop-regulator";
[all …]
Dimx6ul.dtsi519 anatop: anatop@020c8000 { label
520 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
528 compatible = "fsl,anatop-regulator";
532 anatop-reg-offset = <0x120>;
533 anatop-vol-bit-shift = <8>;
534 anatop-vol-bit-width = <5>;
535 anatop-min-bit-val = <0>;
536 anatop-min-voltage = <2625000>;
537 anatop-max-voltage = <3400000>;
538 anatop-enable-bit = <0>;
[all …]
Dimx6ull.dtsi612 anatop: anatop@020c8000 { label
613 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
621 compatible = "fsl,anatop-regulator";
625 anatop-reg-offset = <0x120>;
626 anatop-vol-bit-shift = <8>;
627 anatop-vol-bit-width = <5>;
628 anatop-min-bit-val = <0>;
629 anatop-min-voltage = <2625000>;
630 anatop-max-voltage = <3400000>;
631 anatop-enable-bit = <0>;
[all …]
Dimx6sll.dtsi501 anatop: anatop@020c8000 { label
502 compatible = "fsl,imx6sll-anatop",
503 "fsl,imx6q-anatop",
511 compatible = "fsl,anatop-regulator";
515 anatop-reg-offset = <0x120>;
516 anatop-vol-bit-shift = <8>;
517 anatop-vol-bit-width = <5>;
518 anatop-min-bit-val = <0>;
519 anatop-min-voltage = <2625000>;
520 anatop-max-voltage = <3400000>;
[all …]
Dimx7s.dtsi546 fsl,tempmon =<&anatop>;
553 anatop: anatop@30360000 { label
554 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
564 compatible = "fsl,anatop-regulator";
568 anatop-reg-offset = <0x210>;
569 anatop-vol-bit-shift = <8>;
570 anatop-vol-bit-width = <5>;
571 anatop-min-bit-val = <8>;
572 anatop-min-voltage = <800000>;
573 anatop-max-voltage = <1200000>;
[all …]
Dfsl-imx8mq.dtsi257 anatop: anatop@30360000 { label
258 compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
/external/u-boot/drivers/thermal/
Dimx_thermal.c54 struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs; in read_cpu_temperature() local
101 writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr); in read_cpu_temperature()
102 writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); in read_cpu_temperature()
105 reg = readl(&anatop->tempsense1); in read_cpu_temperature()
108 writel(reg, &anatop->tempsense1); in read_cpu_temperature()
111 writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr); in read_cpu_temperature()
112 writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); in read_cpu_temperature()
113 writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set); in read_cpu_temperature()
116 while ((readl(&anatop->tempsense0) & in read_cpu_temperature()
121 reg = readl(&anatop->tempsense0); in read_cpu_temperature()
[all …]
/external/u-boot/arch/arm/mach-imx/mx6/
Dsoc.c68 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in get_cpu_rev() local
69 u32 reg = readl(&anatop->digprog_sololite); in get_cpu_rev()
74 reg = readl(&anatop->digprog); in get_cpu_rev()
229 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in clear_ldo_ramp() local
236 reg = readl(&anatop->ana_misc2); in clear_ldo_ramp()
238 writel(reg, &anatop->ana_misc2); in clear_ldo_ramp()
250 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in set_ldo_voltage() local
251 u32 val, step, old, reg = readl(&anatop->reg_core); in set_ldo_voltage()
287 writel(reg, &anatop->reg_core); in set_ldo_voltage()
328 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in init_bandgap() local
[all …]
Dclock.c910 struct anatop_regs __iomem *anatop = in enable_fec_anatop_clock() local
916 reg = readl(&anatop->pll_enet); in enable_fec_anatop_clock()
934 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
936 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) in enable_fec_anatop_clock()
949 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
1194 struct anatop_regs __iomem *anatop = in enable_pll3() local
1198 if ((readl(&anatop->usb1_pll_480_ctrl) & in enable_pll3()
1202 &anatop->usb1_pll_480_ctrl_set); in enable_pll3()
1203 writel(0x80, &anatop->ana_misc2_clr); in enable_pll3()
1205 while ((readl(&anatop->usb1_pll_480_ctrl) & in enable_pll3()
[all …]
/external/u-boot/drivers/usb/host/
Dehci-mx6.c86 struct anatop_regs __iomem *anatop = in usb_power_config() local
94 chrg_detect = &anatop->usb1_chrg_detect; in usb_power_config()
95 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; in usb_power_config()
96 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set; in usb_power_config()
99 chrg_detect = &anatop->usb2_chrg_detect; in usb_power_config()
100 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr; in usb_power_config()
101 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set; in usb_power_config()
/external/u-boot/board/udoo/neo/
Dneo.c272 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in setup_fec() local
284 reg = readl(&anatop->pll_enet); in setup_fec()
286 writel(reg, &anatop->pll_enet); in setup_fec()
/external/u-boot/board/freescale/mx6sxsabresd/
Dmx6sxsabresd.c110 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in setup_fec() local
133 reg = readl(&anatop->pll_enet); in setup_fec()
135 writel(reg, &anatop->pll_enet); in setup_fec()