| /external/libhevc/ |
| D | Android.bp | 96 "decoder/arm",
97 "common/arm",
103 "decoder/arm/ihevcd_function_selector.c",
104 "decoder/arm/ihevcd_function_selector_noneon.c",
106 "common/arm/ihevc_intra_pred_filters_neon_intr.c",
107 "common/arm/ihevc_weighted_pred_neon_intr.c",
176 arm: {
178 "decoder/arm",
179 "common/arm",
183 "decoder/arm/ihevcd_function_selector.c",
[all …]
|
| /external/capstone/arch/ARM/ |
| D | ARMInstPrinter.c | 129 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; in set_mem_access()
130 …MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALI… in set_mem_access()
131 …MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVAL… in set_mem_access()
132 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; in set_mem_access()
133 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; in set_mem_access()
136 MI->flat_insn->detail->arm.op_count++; in set_mem_access()
143 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; in op_addImm()
144 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; in op_addImm()
145 MI->flat_insn->detail->arm.op_count++; in op_addImm()
189 …MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter… in printRegImmShift()
[all …]
|
| /external/compiler-rt/lib/builtins/ |
| D | CMakeLists.txt | 259 arm/adddf3vfp.S
260 arm/addsf3vfp.S
261 arm/aeabi_cdcmp.S
262 arm/aeabi_cdcmpeq_check_nan.c
263 arm/aeabi_cfcmp.S
264 arm/aeabi_cfcmpeq_check_nan.c
265 arm/aeabi_dcmp.S
266 arm/aeabi_div0.c
267 arm/aeabi_drsub.c
268 arm/aeabi_fcmp.S
[all …]
|
| /external/u-boot/arch/arm/dts/ |
| D | thunderx-88xx.dtsi | 16 compatible = "arm,psci-0.2";
26 compatible = "cavium,thunder", "arm,armv8";
32 compatible = "cavium,thunder", "arm,armv8";
38 compatible = "cavium,thunder", "arm,armv8";
44 compatible = "cavium,thunder", "arm,armv8";
50 compatible = "cavium,thunder", "arm,armv8";
56 compatible = "cavium,thunder", "arm,armv8";
62 compatible = "cavium,thunder", "arm,armv8";
68 compatible = "cavium,thunder", "arm,armv8";
74 compatible = "cavium,thunder", "arm,armv8";
[all …]
|
| D | hi6220.dtsi | 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 compatible = "arm,psci-0.2";
57 compatible = "arm,cortex-a53", "arm,armv8";
64 compatible = "arm,cortex-a53", "arm,armv8";
71 compatible = "arm,cortex-a53", "arm,armv8";
78 compatible = "arm,cortex-a53", "arm,armv8";
85 compatible = "arm,cortex-a53", "arm,armv8";
92 compatible = "arm,cortex-a53", "arm,armv8";
99 compatible = "arm,cortex-a53", "arm,armv8";
106 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
|
| D | hi3798cv200.dtsi | 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 compatible = "arm,psci-0.2";
28 compatible = "arm,cortex-a53";
35 compatible = "arm,cortex-a53";
42 compatible = "arm,cortex-a53";
49 compatible = "arm,cortex-a53";
57 compatible = "arm,gic-400";
66 compatible = "arm,armv8-timer";
108 compatible = "arm,pl011", "arm,primecell";
117 compatible = "arm,pl011", "arm,primecell";
[all …]
|
| /external/capstone/cstool/ |
| D | cstool_arm.c | 10 cs_arm *arm; in print_insn_detail_arm() local
17 arm = &(ins->detail->arm); in print_insn_detail_arm()
19 if (arm->op_count) in print_insn_detail_arm()
20 printf("\top_count: %u\n", arm->op_count); in print_insn_detail_arm()
22 for (i = 0; i < arm->op_count; i++) { in print_insn_detail_arm()
23 cs_arm_op *op = &(arm->operands[i]); in print_insn_detail_arm()
87 if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) in print_insn_detail_arm()
88 printf("\tCode condition: %u\n", arm->cc); in print_insn_detail_arm()
90 if (arm->update_flags) in print_insn_detail_arm()
93 if (arm->writeback) in print_insn_detail_arm()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 13 %tmp = call i32 @llvm.arm.ssat(i32 %a, i32 32)
21 %tmp = call i32 @llvm.arm.ssat(i32 %a, i32 1)
29 %tmp = call i32 @llvm.arm.usat(i32 %a, i32 31)
37 %tmp = call i32 @llvm.arm.usat(i32 %a, i32 0)
45 %tmp = call i32 @llvm.arm.ssat16(i32 %a, i32 1)
46 %tmp2 = call i32 @llvm.arm.ssat16(i32 %tmp, i32 16)
54 %tmp = call i32 @llvm.arm.usat16(i32 %a, i32 0)
55 %tmp2 = call i32 @llvm.arm.usat16(i32 %tmp, i32 15)
65 %tmp = call i32 @llvm.arm.sxtab16(i32 %a, i32 %b)
66 %tmp1 = call i32 @llvm.arm.sxtb16(i32 %tmp)
[all …]
|
| D | intrinsics-coprocessor.ll | 6 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
8 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
10 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
12 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
14 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
16 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
18 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
20 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
22 tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
24 tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
[all …]
|
| D | misched-fusion-aes.ll | 3 declare <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d, <16 x i8> %k)
4 declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %d)
5 declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d, <16 x i8> %k)
6 declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %d)
17 %e00 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d0, <16 x i8> %k0)
18 %f00 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e00)
19 %e01 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d1, <16 x i8> %k0)
20 %f01 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e01)
21 %e02 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d2, <16 x i8> %k0)
22 %f02 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e02)
[all …]
|
| D | acle-intrinsics-v5.ll | 11 %tmp = call i32 @llvm.arm.smulbb(i32 %a, i32 %b)
18 %tmp = call i32 @llvm.arm.smulbt(i32 %a, i32 %b)
25 %tmp = call i32 @llvm.arm.smultb(i32 %a, i32 %b)
32 %tmp = call i32 @llvm.arm.smultt(i32 %a, i32 %b)
39 %tmp = call i32 @llvm.arm.smulwb(i32 %a, i32 %b)
46 %tmp = call i32 @llvm.arm.smulwt(i32 %a, i32 %b)
58 %acc1 = call i32 @llvm.arm.smlabb(i32 %a, i32 %b, i32 %acc)
59 %acc2 = call i32 @llvm.arm.smlabt(i32 %a, i32 %b, i32 %acc1)
60 %acc3 = call i32 @llvm.arm.smlatb(i32 %a, i32 %b, i32 %acc2)
61 %acc4 = call i32 @llvm.arm.smlatt(i32 %a, i32 %b, i32 %acc3)
[all …]
|
| D | intrinsics-crypto.ll | 6 %tmp3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %tmp, <16 x i8> %tmp2)
8 %tmp4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %tmp3, <16 x i8> %tmp2)
10 %tmp5 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %tmp4)
12 %tmp6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %tmp5)
22 %resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar)
25 %res2 = call <4 x i32> @llvm.arm.neon.sha1c(<4 x i32> %tmp2, i32 %scalar, <4 x i32> %res1)
27 %res3 = call <4 x i32> @llvm.arm.neon.sha1m(<4 x i32> %res2, i32 %scalar, <4 x i32> %res1)
29 %res4 = call <4 x i32> @llvm.arm.neon.sha1p(<4 x i32> %res3, i32 %scalar, <4 x i32> %res1)
31 %res5 = call <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32> %res4, <4 x i32> %tmp3, <4 x i32> %res1)
33 %res6 = call <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32> %res5, <4 x i32> %res1)
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | intrinsics-coprocessor.ll | 7 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
9 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
13 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
15 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
17 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
19 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
21 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
23 tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
25 tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
[all …]
|
| D | intrinsics-crypto.ll | 6 %tmp3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %tmp, <16 x i8> %tmp2)
8 %tmp4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %tmp3, <16 x i8> %tmp2)
10 %tmp5 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %tmp4)
12 %tmp6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %tmp5)
22 %resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar)
25 %res2 = call <4 x i32> @llvm.arm.neon.sha1c(<4 x i32> %tmp2, i32 %scalar, <4 x i32> %res1)
27 %res3 = call <4 x i32> @llvm.arm.neon.sha1m(<4 x i32> %res2, i32 %scalar, <4 x i32> %res1)
29 %res4 = call <4 x i32> @llvm.arm.neon.sha1p(<4 x i32> %res3, i32 %scalar, <4 x i32> %res1)
31 %res5 = call <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32> %res4, <4 x i32> %tmp3, <4 x i32> %res1)
33 %res6 = call <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32> %res5, <4 x i32> %res1)
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/ |
| D | intrinsics-coprocessor.ll | 5 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
7 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
9 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
11 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
13 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
15 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
17 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
19 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
21 tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
23 tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
[all …]
|
| /external/u-boot/doc/ |
| D | README.scrapyard | 20 da830evm arm arm926ejs d7e8b2b9 2015-09-12 Nick Thompson <nick.thompson@ge…
21 wireless_space arm arm926ejs b352182a 2015-09-12 Albert ARIBAUD <albert.u.boot@a…
31 balloon3 arm pxa 679d4456 2015-08-30 Marek Vasut <marex@denx.de>
32 cpu9260_128M arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
33 cpu9260 arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
34 cpu9260_nand_128M arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
35 cpu9260_nand arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
36 cpu9G20_128M arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
37 cpu9G20 arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
38 cpuat91 arm arm920t af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
[all …]
|
| /external/libavc/ |
| D | Android.bp | 67 arm: {
69 "decoder/arm",
70 "common/arm",
74 "decoder/arm/ih264d_function_selector.c",
75 "common/arm/ih264_arm_memory_barrier.s",
88 "decoder/arm/ih264d_function_selector_a9q.c",
89 "common/arm/ih264_intra_pred_chroma_a9q.s",
90 "common/arm/ih264_intra_pred_luma_16x16_a9q.s",
91 "common/arm/ih264_intra_pred_luma_4x4_a9q.s",
92 "common/arm/ih264_intra_pred_luma_8x8_a9q.s",
[all …]
|
| /external/libvpx/libvpx/vpx_dsp/ |
| D | vpx_dsp.mk | 60 DSP_SRCS-$(HAVE_NEON) += arm/highbd_intrapred_neon.c
69 DSP_SRCS-$(HAVE_NEON) += arm/deblock_neon.c
76 DSP_SRCS-$(HAVE_NEON_ASM) += arm/intrapred_neon_asm$(ASM)
77 DSP_SRCS-$(HAVE_NEON) += arm/intrapred_neon.c
107 DSP_SRCS-$(HAVE_NEON) += arm/highbd_vpx_convolve_copy_neon.c
108 DSP_SRCS-$(HAVE_NEON) += arm/highbd_vpx_convolve_avg_neon.c
109 DSP_SRCS-$(HAVE_NEON) += arm/highbd_vpx_convolve8_neon.c
110 DSP_SRCS-$(HAVE_NEON) += arm/highbd_vpx_convolve_neon.c
114 DSP_SRCS-$(HAVE_NEON) += arm/vpx_scaled_convolve8_neon.c
118 DSP_SRCS-yes += arm/vpx_convolve_copy_neon_asm$(ASM)
[all …]
|
| /external/u-boot/board/engicam/imx6q/ |
| D | MAINTAINERS | 12 F: arch/arm/dts/imx6qdl.dtsi
13 F: arch/arm/dts/imx6qdl-u-boot.dtsi
14 F: arch/arm/dts/imx6qdl-icore.dtsi
15 F: arch/arm/dts/imx6qdl-icore-u-boot.dtsi
16 F: arch/arm/dts/imx6q-icore.dts
17 F: arch/arm/dts/imx6q-icore-u-boot.dtsi
18 F: arch/arm/dts/imx6dl-icore.dts
19 F: arch/arm/dts/imx6dl-icore-u-boot.dtsi
20 F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
21 F: arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi
[all …]
|
| /external/capstone/tests/ |
| D | test_arm.c | 35 cs_arm *arm; in print_insn_detail() local
42 arm = &(ins->detail->arm); in print_insn_detail()
44 if (arm->op_count) in print_insn_detail()
45 printf("\top_count: %u\n", arm->op_count); in print_insn_detail()
47 for (i = 0; i < arm->op_count; i++) { in print_insn_detail()
48 cs_arm_op *op = &(arm->operands[i]); in print_insn_detail()
112 if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) in print_insn_detail()
113 printf("\tCode condition: %u\n", arm->cc); in print_insn_detail()
115 if (arm->update_flags) in print_insn_detail()
118 if (arm->writeback) in print_insn_detail()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/BasicAA/ |
| D | cs-cs-arm.ll | 2 ; REQUIRES: arm
5 target triple = "arm-apple-ios"
7 declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly
8 declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind
13 %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) nounwind
14 call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %q, <8 x i16> %y, i32 16)
15 %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) nounwind
22 ; CHECK: Just Ref (MustAlias): Ptr: i8* %p <-> %a = call <8 x i16> @llvm.arm.neon.vld1.v8i…
23 ; CHECK: NoModRef: Ptr: i8* %q <-> %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* …
24 ; CHECK: NoModRef: Ptr: i8* %p <-> call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %q, <8 x i…
[all …]
|
| /external/libvpx/ |
| D | Android.bp | 6 "libvpx/vp8/common/arm/loopfilter_arm.c",
7 "libvpx/vp8/common/arm/neon/bilinearpredict_neon.c",
8 "libvpx/vp8/common/arm/neon/copymem_neon.c",
9 "libvpx/vp8/common/arm/neon/dc_only_idct_add_neon.c",
10 "libvpx/vp8/common/arm/neon/dequant_idct_neon.c",
11 "libvpx/vp8/common/arm/neon/dequantizeb_neon.c",
12 "libvpx/vp8/common/arm/neon/idct_blk_neon.c",
13 "libvpx/vp8/common/arm/neon/iwalsh_neon.c",
14 "libvpx/vp8/common/arm/neon/loopfiltersimplehorizontaledge_neon.c",
15 "libvpx/vp8/common/arm/neon/loopfiltersimpleverticaledge_neon.c",
[all …]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vabs.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
7 %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
15 %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
23 %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
31 %tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
39 %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
47 %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
55 %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
63 %tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
67 declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnone
[all …]
|
| D | vcnt.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
7 %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
15 %tmp2 = call <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8> %tmp1)
19 declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
20 declare <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8>) nounwind readnone
26 %tmp2 = call <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8> %tmp1)
34 %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
42 %tmp2 = call <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32> %tmp1)
50 %tmp2 = call <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8> %tmp1)
58 %tmp2 = call <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16> %tmp1)
[all …]
|
| D | intrinsics.ll | 7 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
9 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
13 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
15 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
17 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
19 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
21 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
25 declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
27 declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
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