Home
last modified time | relevance | path

Searched refs:b000 (Results 1 – 25 of 78) sorted by relevance

1234

/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
47 def : AT<"S1E1RP", 0b01, 0b000, 0b0111, 0b1001, 0b000>;
48 def : AT<"S1E1WP", 0b01, 0b000, 0b0111, 0b1001, 0b001>;
95 def : DC<"IVAC", 0b01, 0b000, 0b0111, 0b0110, 0b001>;
96 def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>;
49 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
50 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
97 def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;
98 def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;
[all …]
DAArch64SVEInstrInfo.td22 defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">;
34 defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">;
38 defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">;
43 defm ADD_ZI : sve_int_arith_imm0<0b000, "add">;
57 defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv">;
59 defm SMAXV_VPZ : sve_int_reduce_1<0b000, "smaxv">;
63 defm ORV_VPZ : sve_int_reduce_2<0b000, "orv">;
77 defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul">;
92 defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb">;
101 defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls">;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonSystemInst.td62 "dccleana($Rs)", [], 0b000, 0b000, 0b0>;
64 "dcinva($Rs)", [], 0b000, 0b000, 0b1>;
66 "dccleaninva($Rs)", [], 0b000, 0b001, 0b0>;
72 "l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>;
DHexagonInstrInfo.td188 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
203 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
221 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
222 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
802 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
[all …]
DHexagonInstrInfoV5.td60 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
65 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
173 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
174 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
177 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
189 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
211 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
272 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
277 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
607 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
[all …]
DHexagonInstrEnc.td486 let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} };
505 let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} };
559 let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} };
573 let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} };
669 let Inst{13-0} = { src2{0}, 0b000, opc{3}, 0, opc{2-0}, dst{4-0} };
712 let Inst{13-0} = { src3{0}, src1{1-0}, 0b000, opc{2-0}, src4{4-0} };
765 let Inst{13-0} = { opc{2}, 0b000, src1{1-0}, opc{1-0}, 1, dst{4-0} };
860 let Inst{13-0} = { 0b0000, src1{1-0}, 0b000, opc{2-0}, dst{1-0} };
863 class V6_pred_and_enc : Enc_COPROC_VX_3op_q<0b000>;
908 let Inst{13-0} = { opc{2}, 0b000000, opc{1}, 0b000, opc{0}, dst{1-0} };
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td105 def FSGNJ_D : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">;
108 def FMIN_D : FPALUD_rr<0b0010101, 0b000, "fmin.d">;
116 def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s"> {
122 def FLE_D : FPCmpD_rr<0b000, "fle.d">;
138 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> {
142 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> {
158 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d"> {
172 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x"> {
DRISCVInstrInfoM.td20 def MUL : ALU_rr<0b0000001, 0b000, "mul">;
31 def MULW : ALUW_rr<0b0000001, 0b000, "mulw">;
DRISCVInstrInfo.td280 : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2),
299 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
304 def BEQ : BranchCC_rri<0b000, "beq">;
311 def LB : Load_ri<0b000, "lb">;
317 def SB : Store_rri<0b000, "sb">;
324 def ADDI : ALU_ri<0b000, "addi">;
336 def ADD : ALU_rr<0b0000000, 0b000, "add">;
337 def SUB : ALU_rr<0b0100000, 0b000, "sub">;
348 def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
359 def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", ""> {
[all …]
DRISCVInstrInfoF.td126 def FSGNJ_S : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">;
129 def FMIN_S : FPALUS_rr<0b0010100, 0b000, "fmin.s">;
142 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w"> {
148 def FLE_S : FPCmpS_rr<0b000, "fle.s">;
164 def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x"> {
/external/syzkaller/pkg/report/testdata/linux/report/
D24130 de40: 974bd151 9f546788 9f546bc8 00000001 00005406 9684b000 20000040 968ce900
31 de60: 20000040 80633638 00005406 9684b000 20000040 968ce900 20000040 8062e6b4
32 de80: 00005406 9684b000 8062e5dc 968ce900 20000040 976d0a40 00000000 8062be58
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td397 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
398 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
399 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
400 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
417 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
418 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
419 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
420 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
422 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
423 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
[all …]
/external/mesa3d/src/intel/compiler/
Dbrw_reg_type.c98 GEN10_ALIGN1_3SRC_REG_TYPE_HF = 0b000,
104 GEN10_ALIGN1_3SRC_REG_TYPE_UD = 0b000,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td395 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
396 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
397 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
398 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
415 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
416 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
417 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
418 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
420 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
421 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
[all …]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-SRS-arm.txt12 # Inst{7-5} = 0b000
/external/libmtp/logs/
Dmtp-detect-samsung-yp-s3.txt59 0240: b400 005f b000 0065 6d00 0066 1c00 006b ..._...em..f...k
64 0290: be00 0053 7c00 0059 b400 005f b000 0065 ...S|..Y..._...e
70 02f0: b400 005f b000 0062 cf00 0066 1c00 006b ..._...b...f...k
86 03f0: be00 0053 7c00 0059 b400 005f b000 0065 ...S|..Y..._...e
124 0240: b400 005f b000 0065 6d00 0066 1c00 006b ..._...em..f...k
129 0290: be00 0053 7c00 0059 b400 005f b000 0065 ...S|..Y..._...e
135 02f0: b400 005f b000 0062 cf00 0066 1c00 006b ..._...b...f...k
151 03f0: be00 0053 7c00 0059 b400 005f b000 0065 ...S|..Y..._...e
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td50 let Inst{7-5} = 0b000;
102 let Inst{7-5} = 0b000;
178 let Inst{7-5} = 0b000;
258 let Inst{7-5} = 0b000;
300 let Inst{7-5} = 0b000;
332 let Inst{7-5} = 0b000;
366 let Inst{7-5} = 0b000;
378 let Inst{7-5} = 0b000;
390 let Inst{7-5} = 0b000;
402 let Inst{7-5} = 0b000;
[all …]
/external/u-boot/doc/
DREADME.fsl-esdhc9 0b000 reserved
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td513 let Inst{14-12} = 0b000; // imm3
591 let Inst{14-12} = 0b000; // imm3
680 let Inst{14-12} = 0b000; // imm3
721 let Inst{14-12} = 0b000; // imm3
843 let Inst{14-12} = 0b000; // imm3
1689 let Inst{14-12} = 0b000;
1783 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1789 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1825 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1902 let Inst{6-4} = 0b000;
[all …]
/external/u-boot/arch/arm/dts/
Dvf.dtsi104 gpio2: gpio@4004b000 {
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td601 let Inst{14-12} = 0b000; // imm3
685 let Inst{14-12} = 0b000; // imm3
806 let Inst{14-12} = 0b000; // imm3
848 let Inst{14-12} = 0b000; // imm3
945 let Inst{14-12} = 0b000; // imm3
1421 let Inst{26-24} = 0b000;
1869 let Inst{14-12} = 0b000;
1973 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1979 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
2033 defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCInstrInfo.td420 def SP_ADD_SP_S : F16_SP_OPS_bconst<0b000, "add_s">;
425 def SP_LD_S : F16_SP_LD<0b000, "ld_s">;
577 def BGT_S : F16_BCC_s7<0b000, "bgt_s">;
611 def ASL_S_ru5 : F16_SH_SUB_BIT_DST<0b000,"asl_s">;
624 F16_OP_HREG_LIMM<0b000, (outs GPR32:$b_s3), (ins i32imm:$LImm),
628 F16_OP_HREG<0b000, (outs GPR32:$b_s3), (ins GPR32:$h),
/external/elfutils/tests/
Drun-readelf-mixed-corenote.sh481 0804a000-0804b000 00001000 4096 /tmp/a.out
712 200001a000-200001b000 00019000 4096 /lib64/ld-2.27.so
713 200001b000-200001c000 0001a000 4096 /lib64/ld-2.27.so
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td607 let Inst{14-12} = 0b000; // imm3
691 let Inst{14-12} = 0b000; // imm3
812 let Inst{14-12} = 0b000; // imm3
854 let Inst{14-12} = 0b000; // imm3
951 let Inst{14-12} = 0b000; // imm3
1412 let Inst{26-24} = 0b000;
1875 let Inst{14-12} = 0b000;
1979 def t2SXTH : T2I_ext_rrot<0b000, "sxth">;
1983 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">;
2073 defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
[all …]

1234