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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td121 def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;
123 def : IC<"IVAU", 0b000, 0b0111, 0b0001, 0b000, 1>;
312 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
314 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
315 def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>;
327 def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>;
328 def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>;
329 def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>;
330 def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>;
331 def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td126 def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;
372 def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;
373 def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;
374 def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
375 def : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>;
376 def : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>;
377 def : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>;
380 def : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>;
381 def : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>;
382 def : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>;
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DAArch64SVEInstrInfo.td129 defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub">;
251 def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">;
280 defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;
326 defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
344 defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>;
362 defm LDFF1B_H : sve_mem_cldff_ss<0b0001, "ldff1b", Z_h, ZPR16, GPR64shifted8>;
409 …defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXT…
431 defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31>;
444 defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31>;
461 defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb">;
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-MOVs-LSL-arm.txt8 # A8.6.89 LSL (register): Inst{7-4} = 0b0001
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td272 defm : int_cond_alias<"e", 0b0001>;
289 defm : int_cond_alias<"eq", 0b0001>; // same as e
290 defm : int_cond_alias<"z", 0b0001>; // same as e
302 defm : fp_cond_alias<"ne", 0b0001>;
313 defm : fp_cond_alias<"nz", 0b0001>; // same as ne
325 defm : cp_cond_alias<"123", 0b0001>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td272 defm : int_cond_alias<"e", 0b0001>;
289 defm : int_cond_alias<"eq", 0b0001>; // same as e
290 defm : int_cond_alias<"z", 0b0001>; // same as e
302 defm : fp_cond_alias<"ne", 0b0001>;
313 defm : fp_cond_alias<"nz", 0b0001>; // same as ne
325 defm : cp_cond_alias<"123", 0b0001>;
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp128 b0001 = 0x1, enumerator
147 { false, false, false, b0001, b1000, b1111, false, NONE },
148 { true, false, false, b0001, b1000, b0000, false, NONE },
149 { true, false, false, b0001, b0001, b1110, false, NONE },
154 { true, true, true, b0010, b1000, b0001, false, NONE },
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td519 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
520 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
521 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
522 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
523 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
524 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
663 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
699 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1413 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1414 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
[all …]
DARMInstrVFP.td426 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
431 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
440 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
445 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
1067 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1072 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1107 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
DARMInstrThumb2.td960 let Inst{26-23} = 0b0001;
1933 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1934 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1935 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1940 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1944 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1945 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2161 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2337 let Inst{7-4} = 0b0001; // Multiply and Subtract
2393 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
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/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td312 class V6_vL32b_cur_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0001>;
331 class V6_vL32b_cur_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0001>;
490 class V6_vL32b_cur_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0001>;
509 class V6_vL32b_cur_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0001>;
820 class V6_vlalignb_enc : Enc_COPROC_VX_4op_r<0b0001>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td1001 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
1002 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
1003 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
1004 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
1005 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
1006 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1144 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1180 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
2003 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2004 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
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DARMInstrVFP.td846 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
851 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
860 def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
946 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
951 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
956 def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,
2073 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2078 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
2123 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
DARMInstrThumb2.td1069 let Inst{26-23} = 0b0001;
2138 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2139 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2140 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2145 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2149 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2150 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2363 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2566 let Inst{7-4} = 0b0001; // Multiply and Subtract
2625 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
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DARMInstrInfo.td2326 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2357 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2477 let Inst{27-24} = 0b0001;
2487 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
3628 let Inst{7-4} = 0b0001;
3642 let Inst{7-4} = 0b0001;
3724 defm EOR : AsI1_bin_irs<0b0001, "eor",
3983 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3996 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
4217 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrNEON.td1024 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
1025 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
1026 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
1027 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
1028 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
1029 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1184 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1220 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
2091 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2092 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
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DARMInstrThumb2.td1080 let Inst{26-23} = 0b0001;
2200 def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>;
2201 def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>;
2202 def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>;
2204 def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>;
2205 def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>;
2206 def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;
2433 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2644 def t2MLS: T2FourRegMLA<0b0001, "mls",
2683 T2SMMUL<0b0001, "smmulr",
[all …]
DARMInstrVFP.td884 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
889 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
898 def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
984 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
990 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
996 def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,
2240 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2246 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
2295 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$src),
DARMInstrInfo.td2436 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2467 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2587 let Inst{27-24} = 0b0001;
2597 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
3774 let Inst{7-4} = 0b0001;
3789 let Inst{7-4} = 0b0001;
3880 defm EOR : AsI1_bin_irs<0b0001, "eor",
4168 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4184 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
4466 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
[all …]
/external/u-boot/board/buffalo/lsxl/
Dkwbimage-lsxhl.cfg182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td349 def ADCRdRr : FRdRr<0b0001,
390 def SUBRdRr : FRdRr<0b0001,
826 def CPSE : FRdRr<0b0001,
833 def CPRdRr : FRdRr<0b0001,
1575 def ROLRd : FRdRr<0b0001,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td383 def ADCRdRr : FRdRr<0b0001,
424 def SUBRdRr : FRdRr<0b0001,
860 def CPSE : FRdRr<0b0001,
867 def CPRdRr : FRdRr<0b0001,
1674 def ROLRd : FRdRr<0b0001,
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td655 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
656 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
667 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
668 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
759 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
760 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
1018 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1019 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1020 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1021 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td653 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
654 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
665 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
666 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
757 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
758 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
1016 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1017 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1018 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1019 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt210 # A8.6.89 LSL (register): Inst{7-4} = 0b0001

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