Searched refs:b0110 (Results 1 – 25 of 42) sorted by relevance
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97 def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;98 def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;391 def : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>;392 def : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>;393 def : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>;394 def : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>;409 def : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>;410 def : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>;415 def : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>;416 def : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>;[all …]
134 defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax">;256 def EORS_PPzPP : sve_int_pred_log<0b0110, "eors">;285 defm LD1H_S_IMM : sve_mem_cld_si<0b0110, "ld1h", Z_s, ZPR32>;331 defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64NoXZRshifted16>;349 defm LDNF1H_S_IMM : sve_mem_cldnf_si<0b0110, "ldnf1h", Z_s, ZPR32>;367 defm LDFF1H_S : sve_mem_cldff_ss<0b0110, "ldff1h", Z_s, ZPR32, GPR64shifted16>;414 defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;423 defm GLD1H_S : sve_mem_32b_gld_sv_32_scaled<0b0110, "ld1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;436 defm GLD1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h", uimm5s2>;449 defm GLD1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h", uimm5s2>;[all …]
95 def : DC<"IVAC", 0b01, 0b000, 0b0111, 0b0110, 0b001>;96 def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>;347 def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>;348 def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;393 def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>;461 def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>;469 def : RWSysReg<"DBGBVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b100>;485 def : RWSysReg<"DBGBCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b101>;501 def : RWSysReg<"DBGWVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b110>;517 def : RWSysReg<"DBGWCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b111>;[all …]
1754 let Inst{24-21} = 0b0110;1976 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;1977 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;1978 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;1979 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;1980 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;1981 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;2314 let Inst{26-23} = 0b0110;2325 let Inst{26-23} = 0b0110;2335 let Inst{26-23} = 0b0110;[all …]
284 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),292 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),737 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {749 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {775 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {786 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {1175 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),1183 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),1633 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {1645 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {[all …]
612 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,682 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,1140 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1943 let Inst{24-21} = 0b0110;2181 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;2182 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;2183 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;2184 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;2185 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;2186 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;2541 let Inst{26-23} = 0b0110;2553 let Inst{26-23} = 0b0110;2564 let Inst{26-23} = 0b0110;[all …]
740 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),748 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),756 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),1218 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {1230 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {1256 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {1267 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {1725 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),1733 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),1741 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),[all …]
699 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr,742 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr,1195 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
866 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,875 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,883 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,2090 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
133 b0110 = 0x6, enumerator155 { true, true, true, b1001, b1001, b0110, false, NONE },158 { false, true, true, b1001, b1001, b0110, true, FILL },161 { false, true, true, b1001, b1001, b0110, true, COPY },
452 # VST1 multi-element, type == 0b0110, align == 0b10 -> undefined457 # VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
282 defm : int_cond_alias<"neg", 0b0110>;297 defm : fp_cond_alias<"g", 0b0110>;320 defm : cp_cond_alias<"2", 0b0110>;
121 let IClass = 0b0110;141 let IClass = 0b0110;
230 let Inst{15-12} = 0b0110;466 let Inst{15-12} = 0b0110;
1950 let Inst{24-21} = 0b0110;2249 def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>;2250 def t2UHADD16 : T2I_pam_intrinsics<0b001, 0b0110, "uhadd16", int_arm_uhadd16>;2251 def t2UHADD8 : T2I_pam_intrinsics<0b000, 0b0110, "uhadd8", int_arm_uhadd8>;2252 def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>;2253 def t2UHSUB16 : T2I_pam_intrinsics<0b101, 0b0110, "uhsub16", int_arm_uhsub16>;2254 def t2UHSUB8 : T2I_pam_intrinsics<0b100, 0b0110, "uhsub8", int_arm_uhsub8>;2624 let Inst{26-23} = 0b0110;2636 let Inst{26-23} = 0b0110;2662 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;[all …]
738 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),746 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),754 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),1258 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {1270 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {1296 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {1307 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {1789 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),1797 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),1805 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),[all …]
716 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr,759 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr,1269 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
904 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,913 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,921 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,2258 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPRnopc:$Rt), (ins),
446 let Inst{27-24} = 0b0110;985 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;1348 let IClass = 0b0110;1373 let IClass = 0b0110;1417 let Inst{27-24} = 0b0110;2503 let Inst{27-24} = 0b0110;4519 let IClass = 0b0110;4539 let IClass = 0b0110;4590 let IClass = 0b0110;4610 let IClass = 0b0110;[all …]
924 def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;925 def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
645 def ORIRdK : FRdK<0b0110,1649 def SBRRdK : FRdK<0b0110,
679 def ORIRdK : FRdK<0b0110,1748 def SBRRdK : FRdK<0b0110,