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Searched refs:brw (Results 1 – 25 of 160) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_urb.c100 static bool check_urb_layout(struct brw_context *brw) in check_urb_layout() argument
102 brw->urb.vs_start = 0; in check_urb_layout()
103 brw->urb.gs_start = brw->urb.nr_vs_entries * brw->urb.vsize; in check_urb_layout()
104 brw->urb.clip_start = brw->urb.gs_start + brw->urb.nr_gs_entries * brw->urb.vsize; in check_urb_layout()
105 brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize; in check_urb_layout()
106 brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize; in check_urb_layout()
108 return brw->urb.cs_start + brw->urb.nr_cs_entries * in check_urb_layout()
109 brw->urb.csize <= brw->urb.size; in check_urb_layout()
116 brw_calculate_urb_fence(struct brw_context *brw, unsigned csize, in brw_calculate_urb_fence() argument
119 const struct gen_device_info *devinfo = &brw->screen->devinfo; in brw_calculate_urb_fence()
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Dbrw_state_upload.c49 brw_upload_initial_gpu_state(struct brw_context *brw) in brw_upload_initial_gpu_state() argument
51 const struct gen_device_info *devinfo = &brw->screen->devinfo; in brw_upload_initial_gpu_state()
57 if (!brw->hw_ctx) in brw_upload_initial_gpu_state()
61 brw_emit_post_sync_nonzero_flush(brw); in brw_upload_initial_gpu_state()
63 brw_upload_invariant_state(brw); in brw_upload_initial_gpu_state()
66 brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS, in brw_upload_initial_gpu_state()
89 brw_load_register_imm32(brw, GEN7_CACHE_MODE_1, in brw_upload_initial_gpu_state()
96 brw_load_register_imm32(brw, GEN7_GT_MODE, in brw_upload_initial_gpu_state()
103 gen8_emit_3dstate_sample_pattern(brw); in brw_upload_initial_gpu_state()
121 brw_get_pipeline_atoms(struct brw_context *brw, in brw_get_pipeline_atoms() argument
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Dbrw_draw.c80 brw_set_prim(struct brw_context *brw, const struct _mesa_prim *prim) in brw_set_prim() argument
82 struct gl_context *ctx = &brw->ctx; in brw_set_prim()
102 if (hw_prim != brw->primitive) { in brw_set_prim()
103 brw->primitive = hw_prim; in brw_set_prim()
104 brw->ctx.NewDriverState |= BRW_NEW_PRIMITIVE; in brw_set_prim()
106 if (reduced_prim[prim->mode] != brw->reduced_primitive) { in brw_set_prim()
107 brw->reduced_primitive = reduced_prim[prim->mode]; in brw_set_prim()
108 brw->ctx.NewDriverState |= BRW_NEW_REDUCED_PRIMITIVE; in brw_set_prim()
114 gen6_set_prim(struct brw_context *brw, const struct _mesa_prim *prim) in gen6_set_prim() argument
116 const struct gl_context *ctx = &brw->ctx; in gen6_set_prim()
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Dbrw_pipe_control.c72 gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags) in gen7_cs_stall_every_four_pipe_controls() argument
74 const struct gen_device_info *devinfo = &brw->screen->devinfo; in gen7_cs_stall_every_four_pipe_controls()
79 brw->pipe_controls_since_last_cs_stall = 0; in gen7_cs_stall_every_four_pipe_controls()
84 if (++brw->pipe_controls_since_last_cs_stall == 4) { in gen7_cs_stall_every_four_pipe_controls()
85 brw->pipe_controls_since_last_cs_stall = 0; in gen7_cs_stall_every_four_pipe_controls()
113 brw_emit_pipe_control(struct brw_context *brw, uint32_t flags, in brw_emit_pipe_control() argument
116 const struct gen_device_info *devinfo = &brw->screen->devinfo; in brw_emit_pipe_control()
135 brw_emit_pipe_control_flush(brw, 0); in brw_emit_pipe_control()
156 bo = brw->workaround_bo; in brw_emit_pipe_control()
185 brw_emit_post_sync_nonzero_flush(brw); in brw_emit_pipe_control()
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Dbrw_curbe.c76 static void calculate_curbe_offsets( struct brw_context *brw ) in calculate_curbe_offsets() argument
78 struct gl_context *ctx = &brw->ctx; in calculate_curbe_offsets()
80 const GLuint nr_fp_regs = (brw->wm.base.prog_data->nr_params + 15) / 16; in calculate_curbe_offsets()
83 const GLuint nr_vp_regs = (brw->vs.base.prog_data->nr_params + 15) / 16; in calculate_curbe_offsets()
110 if (nr_fp_regs > brw->curbe.wm_size || in calculate_curbe_offsets()
111 nr_vp_regs > brw->curbe.vs_size || in calculate_curbe_offsets()
112 nr_clip_regs != brw->curbe.clip_size || in calculate_curbe_offsets()
113 (total_regs < brw->curbe.total_size / 4 && in calculate_curbe_offsets()
114 brw->curbe.total_size > 16)) { in calculate_curbe_offsets()
121 brw->curbe.wm_start = reg; in calculate_curbe_offsets()
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Dbrw_binding_tables.c54 brw_upload_binding_table(struct brw_context *brw, in brw_upload_binding_table() argument
59 const struct gen_device_info *devinfo = &brw->screen->devinfo; in brw_upload_binding_table()
71 brw, &stage_state->surf_offset[ in brw_upload_binding_table()
73 brw->shader_time.bo, 0, ISL_FORMAT_RAW, in brw_upload_binding_table()
74 brw->shader_time.bo->size, 1, RELOC_WRITE); in brw_upload_binding_table()
77 brw_state_batch(brw, prog_data->binding_table.size_bytes, in brw_upload_binding_table()
85 brw->ctx.NewDriverState |= BRW_NEW_BINDING_TABLE_POINTERS; in brw_upload_binding_table()
105 brw_vs_upload_binding_table(struct brw_context *brw) in brw_vs_upload_binding_table() argument
108 const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data; in brw_vs_upload_binding_table()
109 brw_upload_binding_table(brw, in brw_vs_upload_binding_table()
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Dbrw_performance_query.c348 dump_perf_queries(struct brw_context *brw) in dump_perf_queries() argument
350 struct gl_context *ctx = &brw->ctx; in dump_perf_queries()
352 brw->perfquery.n_active_oa_queries, brw->perfquery.n_oa_users); in dump_perf_queries()
353 _mesa_HashWalk(ctx->PerfQuery.Objects, dump_perf_query_callback, brw); in dump_perf_queries()
359 get_free_sample_buf(struct brw_context *brw) in get_free_sample_buf() argument
361 struct exec_node *node = exec_list_pop_head(&brw->perfquery.free_sample_buffers); in get_free_sample_buf()
367 buf = ralloc_size(brw, sizeof(*buf)); in get_free_sample_buf()
378 reap_old_sample_buffers(struct brw_context *brw) in reap_old_sample_buffers() argument
381 exec_list_get_tail(&brw->perfquery.sample_buffers); in reap_old_sample_buffers()
391 &brw->perfquery.sample_buffers) in reap_old_sample_buffers()
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Dintel_batchbuffer.c56 intel_batchbuffer_reset(struct brw_context *brw);
80 intel_batchbuffer_init(struct brw_context *brw) in intel_batchbuffer_init() argument
82 struct intel_screen *screen = brw->screen; in intel_batchbuffer_init()
83 struct intel_batchbuffer *batch = &brw->batch; in intel_batchbuffer_init()
117 intel_batchbuffer_reset(brw); in intel_batchbuffer_init()
164 recreate_growing_buffer(struct brw_context *brw, in recreate_growing_buffer() argument
168 struct intel_screen *screen = brw->screen; in recreate_growing_buffer()
169 struct intel_batchbuffer *batch = &brw->batch; in recreate_growing_buffer()
179 grow->map = brw_bo_map(brw, grow->bo, MAP_READ | MAP_WRITE); in recreate_growing_buffer()
183 intel_batchbuffer_reset(struct brw_context *brw) in intel_batchbuffer_reset() argument
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DgenX_blorp_exec.c45 struct brw_context *brw = batch->driver_batch; in blorp_emit_dwords() local
47 intel_batchbuffer_begin(brw, n, RENDER_RING); in blorp_emit_dwords()
48 uint32_t *map = brw->batch.map_next; in blorp_emit_dwords()
49 brw->batch.map_next += n; in blorp_emit_dwords()
50 intel_batchbuffer_advance(brw); in blorp_emit_dwords()
59 struct brw_context *brw = batch->driver_batch; in blorp_emit_reloc() local
62 if (GEN_GEN < 6 && brw_ptr_in_state_buffer(&brw->batch, location)) { in blorp_emit_reloc()
63 offset = (char *)location - (char *)brw->batch.state.map; in blorp_emit_reloc()
64 return brw_state_reloc(&brw->batch, offset, in blorp_emit_reloc()
69 assert(!brw_ptr_in_state_buffer(&brw->batch, location)); in blorp_emit_reloc()
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Dbrw_state.h100 brw_state_dirty(const struct brw_context *brw, in brw_state_dirty() argument
103 return ((brw->NewGLState & mesa_flags) | in brw_state_dirty()
104 (brw->ctx.NewDriverState & brw_flags)) != 0; in brw_state_dirty()
108 void brw_upload_binding_table(struct brw_context *brw,
114 void brw_upload_invariant_state(struct brw_context *brw);
116 brw_depthbuffer_format(struct brw_context *brw);
121 void brw_upload_state_base_address(struct brw_context *brw);
124 void gen8_write_pma_stall_bits(struct brw_context *brw,
128 void brw_disk_cache_init(struct brw_context *brw);
129 bool brw_disk_cache_upload_program(struct brw_context *brw,
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Dbrw_compute.c38 prepare_indirect_gpgpu_walker(struct brw_context *brw) in prepare_indirect_gpgpu_walker() argument
40 const struct gen_device_info *devinfo = &brw->screen->devinfo; in prepare_indirect_gpgpu_walker()
41 GLintptr indirect_offset = brw->compute.num_work_groups_offset; in prepare_indirect_gpgpu_walker()
42 struct brw_bo *bo = brw->compute.num_work_groups_bo; in prepare_indirect_gpgpu_walker()
44 brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0); in prepare_indirect_gpgpu_walker()
45 brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4); in prepare_indirect_gpgpu_walker()
46 brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8); in prepare_indirect_gpgpu_walker()
63 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0); in prepare_indirect_gpgpu_walker()
74 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4); in prepare_indirect_gpgpu_walker()
85 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8); in prepare_indirect_gpgpu_walker()
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Dbrw_queryobj.c46 brw_timebase_scale(struct brw_context *brw, uint64_t gpu_timestamp) in brw_timebase_scale() argument
48 const struct gen_device_info *devinfo = &brw->screen->devinfo; in brw_timebase_scale()
65 brw_raw_timestamp_delta(struct brw_context *brw, uint64_t time0, uint64_t time1) in brw_raw_timestamp_delta() argument
67 if (brw->screen->hw_has_timestamp == 2) { in brw_raw_timestamp_delta()
85 brw_write_timestamp(struct brw_context *brw, struct brw_bo *query_bo, int idx) in brw_write_timestamp() argument
87 const struct gen_device_info *devinfo = &brw->screen->devinfo; in brw_write_timestamp()
91 brw_emit_pipe_control_flush(brw, in brw_write_timestamp()
101 brw_emit_pipe_control_write(brw, flags, in brw_write_timestamp()
109 brw_write_depth_count(struct brw_context *brw, struct brw_bo *query_bo, int idx) in brw_write_depth_count() argument
111 const struct gen_device_info *devinfo = &brw->screen->devinfo; in brw_write_depth_count()
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Dbrw_wm_surface_state.c79 get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt, in get_isl_surf() argument
86 const struct gen_device_info *devinfo = &brw->screen->devinfo; in get_isl_surf()
135 brw_emit_surface_state(struct brw_context *brw, in brw_emit_surface_state() argument
142 const struct gen_device_info *devinfo = &brw->screen->devinfo; in brw_emit_surface_state()
149 get_isl_surf(brw, mt, target, &view, &tile_x, &tile_y, &offset, &surf); in brw_emit_surface_state()
182 void *state = brw_state_batch(brw, in brw_emit_surface_state()
183 brw->isl_dev.ss.size, in brw_emit_surface_state()
184 brw->isl_dev.ss.align, in brw_emit_surface_state()
187 isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view, in brw_emit_surface_state()
188 .address = brw_state_reloc(&brw->batch, in brw_emit_surface_state()
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Dbrw_misc_state.c55 upload_pipelined_state_pointers(struct brw_context *brw) in upload_pipelined_state_pointers() argument
57 const struct gen_device_info *devinfo = &brw->screen->devinfo; in upload_pipelined_state_pointers()
68 OUT_RELOC(brw->batch.state.bo, 0, brw->vs.base.state_offset); in upload_pipelined_state_pointers()
69 if (brw->ff_gs.prog_active) in upload_pipelined_state_pointers()
70 OUT_RELOC(brw->batch.state.bo, 0, brw->ff_gs.state_offset | 1); in upload_pipelined_state_pointers()
73 OUT_RELOC(brw->batch.state.bo, 0, brw->clip.state_offset | 1); in upload_pipelined_state_pointers()
74 OUT_RELOC(brw->batch.state.bo, 0, brw->sf.state_offset); in upload_pipelined_state_pointers()
75 OUT_RELOC(brw->batch.state.bo, 0, brw->wm.base.state_offset); in upload_pipelined_state_pointers()
76 OUT_RELOC(brw->batch.state.bo, 0, brw->cc.state_offset); in upload_pipelined_state_pointers()
79 brw->ctx.NewDriverState |= BRW_NEW_PSP; in upload_pipelined_state_pointers()
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Dbrw_conditional_render.c41 set_predicate_enable(struct brw_context *brw, in set_predicate_enable() argument
45 brw->predicate.state = BRW_PREDICATE_STATE_RENDER; in set_predicate_enable()
47 brw->predicate.state = BRW_PREDICATE_STATE_DONT_RENDER; in set_predicate_enable()
51 set_predicate_for_overflow_query(struct brw_context *brw, in set_predicate_for_overflow_query() argument
55 if (!can_do_mi_math_and_lrr(brw->screen)) { in set_predicate_for_overflow_query()
56 brw->predicate.state = BRW_PREDICATE_STATE_STALL_FOR_QUERY; in set_predicate_for_overflow_query()
60 brw->predicate.state = BRW_PREDICATE_STATE_USE_BIT; in set_predicate_for_overflow_query()
66 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in set_predicate_for_overflow_query()
68 hsw_overflow_result_to_gpr0(brw, query, count); in set_predicate_for_overflow_query()
69 brw_load_register_reg64(brw, HSW_CS_GPR(0), MI_PREDICATE_SRC0); in set_predicate_for_overflow_query()
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Dbrw_disk_cache.c43 gen_shader_sha1(struct brw_context *brw, struct gl_program *prog, in gen_shader_sha1() argument
111 read_and_upload(struct brw_context *brw, struct disk_cache *cache, in read_and_upload() argument
120 brw_vs_populate_key(brw, &prog_key.vs); in read_and_upload()
128 brw_tcs_populate_key(brw, &prog_key.tcs); in read_and_upload()
132 brw_tes_populate_key(brw, &prog_key.tes); in read_and_upload()
136 brw_gs_populate_key(brw, &prog_key.gs); in read_and_upload()
140 brw_wm_populate_key(brw, &prog_key.wm); in read_and_upload()
144 brw_cs_populate_key(brw, &prog_key.cs); in read_and_upload()
151 gen_shader_sha1(brw, prog, stage, &prog_key, binary_sha1); in read_and_upload()
156 if (brw->ctx._Shader->Flags & GLSL_CACHE_INFO) { in read_and_upload()
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Dintel_upload.c48 intel_upload_finish(struct brw_context *brw) in intel_upload_finish() argument
50 assert((brw->upload.bo == NULL) == (brw->upload.map == NULL)); in intel_upload_finish()
51 if (!brw->upload.bo) in intel_upload_finish()
54 brw_bo_unmap(brw->upload.bo); in intel_upload_finish()
55 brw_bo_unreference(brw->upload.bo); in intel_upload_finish()
56 brw->upload.bo = NULL; in intel_upload_finish()
57 brw->upload.map = NULL; in intel_upload_finish()
58 brw->upload.next_offset = 0; in intel_upload_finish()
85 intel_upload_space(struct brw_context *brw, in intel_upload_space() argument
93 offset = ALIGN_NPOT(brw->upload.next_offset, alignment); in intel_upload_space()
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Dbrw_context.c132 const struct brw_context *const brw = brw_context(ctx); in intel_get_string() local
140 (GLubyte *) brw_get_renderer_string(brw->screen); in intel_get_string()
150 struct brw_context *brw = brw_context(ctx); in intel_viewport() local
151 __DRIcontext *driContext = brw->driContext; in intel_viewport()
165 struct brw_context *brw = brw_context(ctx); in intel_update_framebuffer() local
170 intel_quantize_num_samples(brw->screen, in intel_update_framebuffer()
178 struct brw_context *brw = brw_context(ctx); in intel_update_state() local
183 brw->NewGLState |= new_state; in intel_update_state()
189 brw->stencil_enabled = _mesa_stencil_is_enabled(ctx); in intel_update_state()
190 brw->stencil_two_sided = _mesa_stencil_is_two_sided(ctx); in intel_update_state()
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Dgen6_sol.c38 gen6_update_sol_surfaces(struct brw_context *brw) in gen6_update_sol_surfaces() argument
40 struct gl_context *ctx = &brw->ctx; in gen6_update_sol_surfaces()
58 if (brw->programs[MESA_SHADER_GEOMETRY]) { in gen6_update_sol_surfaces()
60 brw, xfb_obj->Buffers[buffer], in gen6_update_sol_surfaces()
61 &brw->gs.base.surf_offset[surf_index], in gen6_update_sol_surfaces()
66 brw, xfb_obj->Buffers[buffer], in gen6_update_sol_surfaces()
67 &brw->ff_gs.surf_offset[surf_index], in gen6_update_sol_surfaces()
72 if (!brw->programs[MESA_SHADER_GEOMETRY]) in gen6_update_sol_surfaces()
73 brw->ff_gs.surf_offset[surf_index] = 0; in gen6_update_sol_surfaces()
75 brw->gs.base.surf_offset[surf_index] = 0; in gen6_update_sol_surfaces()
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Dgen7_urb.c63 gen7_allocate_push_constants(struct brw_context *brw) in gen7_allocate_push_constants() argument
65 const struct gen_device_info *devinfo = &brw->screen->devinfo; in gen7_allocate_push_constants()
68 bool gs_present = brw->programs[MESA_SHADER_GEOMETRY]; in gen7_allocate_push_constants()
71 bool tess_present = brw->programs[MESA_SHADER_TESS_EVAL]; in gen7_allocate_push_constants()
91 gen7_emit_push_constant_state(brw, multiplier * vs_size, in gen7_allocate_push_constants()
106 brw->vs.base.push_constants_dirty = true; in gen7_allocate_push_constants()
107 brw->tcs.base.push_constants_dirty = true; in gen7_allocate_push_constants()
108 brw->tes.base.push_constants_dirty = true; in gen7_allocate_push_constants()
109 brw->gs.base.push_constants_dirty = true; in gen7_allocate_push_constants()
110 brw->wm.base.push_constants_dirty = true; in gen7_allocate_push_constants()
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Dbrw_gs.c39 brw_gs_debug_recompile(struct brw_context *brw, struct gl_program *prog, in brw_gs_debug_recompile() argument
46 brw_find_previous_compile(&brw->cache, BRW_CACHE_GS_PROG, in brw_gs_debug_recompile()
55 found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex); in brw_gs_debug_recompile()
77 brw_codegen_gs_prog(struct brw_context *brw, in brw_codegen_gs_prog() argument
81 struct brw_compiler *compiler = brw->screen->compiler; in brw_codegen_gs_prog()
82 const struct gen_device_info *devinfo = &brw->screen->devinfo; in brw_codegen_gs_prog()
83 struct brw_stage_state *stage_state = &brw->gs.base; in brw_codegen_gs_prog()
108 st_index = brw_get_shader_time_index(brw, &gp->program, ST_GS, true); in brw_codegen_gs_prog()
110 if (unlikely(brw->perf_debug)) { in brw_codegen_gs_prog()
111 start_busy = brw->batch.last_bo && brw_bo_busy(brw->batch.last_bo); in brw_codegen_gs_prog()
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DgenX_state_upload.c60 emit_dwords(struct brw_context *brw, unsigned n) in emit_dwords() argument
62 intel_batchbuffer_begin(brw, n, RENDER_RING); in emit_dwords()
63 uint32_t *map = brw->batch.map_next; in emit_dwords()
64 brw->batch.map_next += n; in emit_dwords()
65 intel_batchbuffer_advance(brw); in emit_dwords()
79 __gen_combine_address(struct brw_context *brw, void *location, in __gen_combine_address() argument
82 struct intel_batchbuffer *batch = &brw->batch; in __gen_combine_address()
89 offset = (char *) location - (char *) brw->batch.state.map; in __gen_combine_address()
97 offset = (char *) location - (char *) brw->batch.batch.map; in __gen_combine_address()
135 KSP(struct brw_context *brw, uint32_t offset) in KSP() argument
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Dgen6_queryobj.c43 set_query_availability(struct brw_context *brw, struct brw_query_object *query, in set_query_availability() argument
61 if (brw->ctx.Extensions.ARB_query_buffer_object && in set_query_availability()
73 brw_emit_pipe_control_write(brw, flags, in set_query_availability()
80 write_primitives_generated(struct brw_context *brw, in write_primitives_generated() argument
83 const struct gen_device_info *devinfo = &brw->screen->devinfo; in write_primitives_generated()
85 brw_emit_mi_flush(brw); in write_primitives_generated()
88 brw_store_register_mem64(brw, query_bo, in write_primitives_generated()
92 brw_store_register_mem64(brw, query_bo, CL_INVOCATION_COUNT, in write_primitives_generated()
98 write_xfb_primitives_written(struct brw_context *brw, in write_xfb_primitives_written() argument
101 const struct gen_device_info *devinfo = &brw->screen->devinfo; in write_xfb_primitives_written()
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Dbrw_program.c66 brw_create_nir(struct brw_context *brw, in brw_create_nir() argument
72 struct gl_context *ctx = &brw->ctx; in brw_create_nir()
102 (stage == MESA_SHADER_TESS_CTRL && brw->screen->devinfo.gen >= 8) || in brw_create_nir()
109 nir = brw_preprocess_nir(brw->screen->compiler, nir); in brw_create_nir()
161 struct brw_context *brw = brw_context(ctx); in brwNewProgram() local
165 prog->id = get_new_program_id(brw->screen); in brwNewProgram()
176 struct brw_context *brw = brw_context(ctx); in brwDeleteProgram() local
202 if (brw->programs[i] == prog) in brwDeleteProgram()
203 brw->programs[i] = (struct gl_program *) &deleted_program; in brwDeleteProgram()
217 struct brw_context *brw = brw_context(ctx); in brwProgramStringNotify() local
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Dgen7_l3_state.c39 get_pipeline_state_l3_weights(const struct brw_context *brw) in get_pipeline_state_l3_weights() argument
42 [MESA_SHADER_VERTEX] = &brw->vs.base, in get_pipeline_state_l3_weights()
43 [MESA_SHADER_TESS_CTRL] = &brw->tcs.base, in get_pipeline_state_l3_weights()
44 [MESA_SHADER_TESS_EVAL] = &brw->tes.base, in get_pipeline_state_l3_weights()
45 [MESA_SHADER_GEOMETRY] = &brw->gs.base, in get_pipeline_state_l3_weights()
46 [MESA_SHADER_FRAGMENT] = &brw->wm.base, in get_pipeline_state_l3_weights()
47 [MESA_SHADER_COMPUTE] = &brw->cs.base in get_pipeline_state_l3_weights()
53 brw->ctx._Shader->CurrentProgram[stage_states[i]->stage]; in get_pipeline_state_l3_weights()
63 return gen_get_default_l3_weights(&brw->screen->devinfo, in get_pipeline_state_l3_weights()
71 setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg) in setup_l3_config() argument
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