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Searched refs:c15 (Results 1 – 25 of 60) sorted by relevance

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/external/u-boot/arch/arm/cpu/armv7/
Dstart.S172 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
174 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
178 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
180 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
184 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
186 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
189 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
191 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
195 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
197 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
[all …]
Dnonsec_virt.S116 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
/external/clang/test/CodeGen/
Dstruct.c138 struct a15 {char a; int b[];} c15; variable
139 int a16(void) {c15.a = 1;} in a16()
/external/u-boot/arch/arm/include/asm/arch-mx35/
Dlowlevel_macro.S116 mcr p15, 0, r0, c15, c2, 4
124 mcr p15, 0, r0, c15, c2, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/SystemZ/
Dregs-good.s128 #CHECK: lctl %c14, %c15, 0 # encoding: [0xb7,0xef,0x00,0x00]
137 lctl %c14,%c15,0
203 #CHECK: .cfi_offset %c15, 438
269 .cfi_offset %c15,438
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dreadcyclecounter.ll4 ; CHECK: r1:0 = c15:14
/external/deqp-deps/glslang/Test/
Dhlsl.buffer.frag25 column_major float3x4 m3 : packoffset(c15);
DstringToDouble.vert71 double c15 = 000120030000.0045600000e4;
/external/u-boot/board/freescale/mx31pdk/
Dlowlevel_init.S14 mcr p15, 0, r0, c15, c2, 4
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-system.txt50 # CHECK: sysl x20, #6, c3, c15, #7
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-system.txt50 # CHECK: sysl x20, #6, c3, c15, #7
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs302 0x12,0xf7,0x7b,0xec = ldcl p7, c15, [r11], #-72
314 0x12,0xf7,0x7b,0x8c = ldclhi p7, c15, [r11], #-72
378 0xd6,0xff,0xff,0xee = mrc p15, #7, apsr_nzcv, c15, c6, #6
380 0x30,0xf9,0xff,0xfe = mrc2 p9, #7, apsr_nzcv, c15, c0, #1
381 0xd6,0xff,0xff,0x0e = mrceq p15, #7, apsr_nzcv, c15, c6, #6
787 0x12,0xf7,0x6b,0xec = stcl p7, c15, [r11], #-72
799 0x12,0xf7,0x6b,0x8c = stclhi p7, c15, [r11], #-72
Dbasic-thumb2-instructions.s.cs242 0x7b,0xec,0x12,0xf7 = ldcl p7, c15, [r11], #-72
481 0xff,0xee,0xd6,0xff = mrc p15, #7, apsr_nzcv, c15, c6, #6
485 0xff,0xfe,0x30,0xf8 = mrc2 p8, #7, apsr_nzcv, c15, c0, #1
861 0x6b,0xec,0x12,0xf7 = stcl p7, c15, [r11], #-72
/external/llvm/test/CodeGen/Mips/
Dra-allocatable.ll78 @c15 = external global i32*
237 %91 = load i32*, i32** @c15, align 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dra-allocatable.ll78 @c15 = external global i32*
237 %91 = load i32*, i32** @c15, align 4
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td162 def UPCH : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>;
174 def UPC : Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>;
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1096 ldcl p7, c15, [r11], #-72
1109 ldclhi p7, c15, [r11], #-72
1137 @ CHECK: ldcl p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0xec]
1150 @ CHECK: ldclhi p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0x8c]
1383 mrc p15, #7, apsr_nzcv, c15, c6, #6
1385 mrc2 p9, #7, apsr_nzcv, c15, c0, #1
1388 @ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee]
1390 @ CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xf9,0xff,0xfe]
1392 mrceq p15, #7, apsr_nzcv, c15, c6, #6
1393 @ CHECK: mrceq p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0x0e]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1098 ldcl p7, c15, [r11], #-72
1111 ldclhi p7, c15, [r11], #-72
1139 @ CHECK: ldcl p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0xec]
1152 @ CHECK: ldclhi p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0x8c]
1385 mrc p15, #7, apsr_nzcv, c15, c6, #6
1387 mrc2 p9, #7, apsr_nzcv, c15, c0, #1
1390 @ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee]
1392 @ CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xf9,0xff,0xfe]
1394 mrceq p15, #7, apsr_nzcv, c15, c6, #6
1395 @ CHECK: mrceq p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0x0e]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td157 def UPCYCLEHI: Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>;
175 def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI], ["upcycle"]>,
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Darith-fp.ll993 %c15 = fadd float %a15, %b15
1009 %r15 = insertelement <16 x float> %r14, float %c15, i32 15
1097 %c15 = fsub float %a15, %b15
1113 %r15 = insertelement <16 x float> %r14, float %c15, i32 15
1201 %c15 = fmul float %a15, %b15
1217 %r15 = insertelement <16 x float> %r14, float %c15, i32 15
1305 %c15 = fdiv float %a15, %b15
1321 %r15 = insertelement <16 x float> %r14, float %c15, i32 15
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s672 ldcl p7, c15, [r11], #-72
685 ldclhi p7, c15, [r11], #-72
713 @ CHECK: ldcl p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0xec]
726 @ CHECK: ldclhi p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0x8c]
1956 stcl p7, c15, [r11], #-72
1969 stclhi p7, c15, [r11], #-72
1997 @ CHECK: stcl p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x6b,0xec]
2010 @ CHECK: stclhi p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x6b,0x8c]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dthumb-tests.txt221 # CHECK: stc2 p12, c15, [r9], {137}
/external/llvm/test/MC/Disassembler/ARM/
Dthumb-tests.txt221 # CHECK: stc2 p12, c15, [r9], {137}
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dthumb-tests.txt221 # CHECK: stc2 p12, c15, [r9], {137}
/external/deqp-deps/glslang/Test/baseResults/
DstringToDouble.vert.out325 0:71 'c15' ( temp double)
849 0:71 'c15' ( temp double)

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