Searched refs:cache_loop (Results 1 – 2 of 2) sorted by relevance
| /external/u-boot/arch/mips/lib/ |
| D | cache.c | 94 #define cache_loop(start, end, lsize, ops...) do { \ macro
121 cache_loop(start_addr, start_addr + size, ilsize, in flush_cache()
127 cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); in flush_cache()
130 cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD); in flush_cache()
133 cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); in flush_cache()
152 cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); in flush_dcache_range()
155 cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); in flush_dcache_range()
171 cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); in invalidate_dcache_range()
173 cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); in invalidate_dcache_range()
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| D | cache_init.S | 44 .macro cache_loop curr, end, line_sz, op macro
313 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
317 cache_loop t0, t1, R_IC_LINE, FILL
320 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
343 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
352 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
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