Searched refs:cfg_tmp (Results 1 – 2 of 2) sorted by relevance
150 u32 cfg_tmp, reg = 0; in setup_serdes_volt() local176 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in setup_serdes_volt()177 cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; in setup_serdes_volt()179 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { in setup_serdes_volt()186 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in setup_serdes_volt()187 cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; in setup_serdes_volt()189 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { in setup_serdes_volt()198 cfg_tmp = (cfg_rcw5 >> 22) & 0x3; in setup_serdes_volt()199 for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { in setup_serdes_volt()214 cfg_tmp = (cfg_rcw5 >> 20) & 0x3; in setup_serdes_volt()[all …]
227 u32 cfg_tmp; in do_enabled_lanes_reset() local235 cfg_tmp = cfg & srds_prctl_info[pos].mask; in do_enabled_lanes_reset()236 cfg_tmp >>= srds_prctl_info[pos].shift; in do_enabled_lanes_reset()238 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { in do_enabled_lanes_reset()344 u32 cfg_tmp; in setup_serdes_volt() local376 cfg_tmp = cfg_rcwsrds1 & 0x3; in setup_serdes_volt()377 do_pll_reset(cfg_tmp, serdes1_base); in setup_serdes_volt()381 cfg_tmp = cfg_rcwsrds1 & 0xC; in setup_serdes_volt()382 cfg_tmp >>= 2; in setup_serdes_volt()383 do_pll_reset(cfg_tmp, serdes2_base); in setup_serdes_volt()[all …]