| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | clock.h | 58 uint clk_div; in clk_get_divisor() local
60 clk_div = input_rate / output_rate; in clk_get_divisor()
61 clk_div = (clk_div + 1) & 0xfffe; in clk_get_divisor()
63 return clk_div; in clk_get_divisor()
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| /external/u-boot/drivers/spi/ |
| D | rk_spi.c | 83 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk() local
92 if (clk_div > 0xfffe) { in rkspi_set_clk()
93 clk_div = 0xfffe; in rkspi_set_clk()
95 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
99 clk_div = (clk_div + 1) & 0xfffe; in rkspi_set_clk()
101 debug("spi speed %u, div %u\n", speed, clk_div); in rkspi_set_clk()
103 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); in rkspi_set_clk()
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| D | designware_spi.c | 443 u16 clk_div; in dw_spi_set_speed() local
452 clk_div = priv->bus_clk_rate / speed; in dw_spi_set_speed()
453 clk_div = (clk_div + 1) & 0xfffe; in dw_spi_set_speed()
454 dw_write(priv, DW_SPI_BAUDR, clk_div); in dw_spi_set_speed()
461 priv->freq, clk_div); in dw_spi_set_speed()
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| D | ti_qspi.c | 118 uint clk_div; in ti_spi_set_speed() local
121 clk_div = 0; in ti_spi_set_speed()
123 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; in ti_spi_set_speed()
126 if (clk_div > QSPI_CLK_DIV_MAX) in ti_spi_set_speed()
127 clk_div = QSPI_CLK_DIV_MAX; in ti_spi_set_speed()
129 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); in ti_spi_set_speed()
135 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_spi_set_speed()
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| /external/u-boot/drivers/video/sunxi/ |
| D | sunxi_lcd.c | 46 int clk_div, clk_double, ret; in sunxi_lcd_enable() local
56 &clk_div, &clk_double, false); in sunxi_lcd_enable()
57 lcdc_tcon0_mode_set(lcdc, edid, clk_div, false, in sunxi_lcd_enable()
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| D | sunxi_display.c | 649 int clk_div, clk_double, pin; local
668 lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
672 lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
678 int *clk_div, int *clk_double, argument
696 lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
751 int clk_div, int clk_double) argument
775 SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
925 int __maybe_unused clk_div, clk_double; local
938 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
939 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
[all …]
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| D | lcdc.c | 72 int clk_div, bool for_ext_vga_dac, in lcdc_tcon0_mode_set() argument
88 SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk); in lcdc_tcon0_mode_set()
212 int *clk_div, int *clk_double, bool is_composite) in lcdc_pll_set() argument
326 *clk_div = best_m; in lcdc_pll_set()
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| /external/u-boot/drivers/led/ |
| D | led_bcm6358.c | 119 unsigned int clk_div; in bcm6358_led_probe() local
128 clk_div = dev_read_u32_default(dev, "brcm,clk-div", in bcm6358_led_probe()
130 switch (clk_div) { in bcm6358_led_probe()
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| /external/u-boot/drivers/i2c/ |
| D | mxc_i2c.c | 140 u8 clk_div; in i2c_imx_get_clk() local
155 clk_div = 0; in i2c_imx_get_clk()
157 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; in i2c_imx_get_clk()
159 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) in i2c_imx_get_clk()
163 return clk_div; in i2c_imx_get_clk()
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| D | s3c24x0_i2c.h | 59 unsigned clk_div; member
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| D | exynos_hs_i2c.c | 166 i2c_bus->clk_div = i; in hsi2c_get_clk_details()
187 n_clkdiv = i2c_bus->clk_div; in hsi2c_ch_init()
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| D | tegra_i2c.c | 117 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; in i2c_init_controller()
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| /external/u-boot/drivers/mmc/ |
| D | exynos_dw_mmc.c | 57 int8_t clk_div; in exynos_dwmci_get_clk() local
65 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) in exynos_dwmci_get_clk()
73 return sclk / clk_div / (host->div + 1); in exynos_dwmci_get_clk()
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| D | meson_gx_mmc.c | 35 unsigned int clk, clk_src, clk_div; in meson_mmc_config_clock() local
48 clk_div = DIV_ROUND_UP(clk, mmc->clock); in meson_mmc_config_clock()
58 meson_mmc_clk |= clk_div; in meson_mmc_config_clock()
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| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| D | lcdc.h | 121 int clk_div, bool for_ext_vga_dac,
127 int dotclock, int *clk_div, int *clk_double,
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| /external/u-boot/arch/arm/include/asm/arch-tegra/ |
| D | tegra_i2c.h | 91 u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */ member
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| /external/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| D | clk-bcm281xx.c | 23 #define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \ argument
29 .div = clk_div, \
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| /external/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| D | clk-bcm235xx.c | 23 #define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \ argument
29 .div = clk_div, \
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| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rk3399.c | 437 #define I2C_CLK_REG_VALUE(bus, clk_div) \ argument
438 ((clk_div - 1) << \
451 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ argument
452 ((clk_div - 1) << \
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