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Searched refs:clock_set_pll3 (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/drivers/video/sunxi/
Dlcdc.c283 clock_set_pll3(297000000); /* Fix the video pll at 297 MHz */ in lcdc_pll_set()
290 clock_set_pll3(best_n * 3000000); in lcdc_pll_set()
Dsunxi_dw_hdmi.c334 clock_set_pll3(297000000); in sunxi_dw_hdmi_probe()
Dsunxi_display.c98 clock_set_pll3(300000000); in sunxi_hdmi_hpd_detect()
137 clock_set_pll3(0); in sunxi_hdmi_shutdown()
/external/u-boot/arch/arm/mach-sunxi/
Dclock_sun4i.c182 void clock_set_pll3(unsigned int clk) in clock_set_pll3() function
Dclock_sun6i.c148 void clock_set_pll3(unsigned int clk) in clock_set_pll3() function
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Dclock_sun4i.h356 void clock_set_pll3(unsigned int hz);
Dclock_sun6i.h514 void clock_set_pll3(unsigned int hz);