| /external/u-boot/drivers/i2c/ |
| D | designware_i2c.c | 80 unsigned int cntl; in __dw_i2c_set_bus_speed() local
94 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); in __dw_i2c_set_bus_speed()
99 cntl |= IC_CON_SPD_SS; in __dw_i2c_set_bus_speed()
113 cntl |= IC_CON_SPD_SS; in __dw_i2c_set_bus_speed()
127 cntl |= IC_CON_SPD_FS; in __dw_i2c_set_bus_speed()
140 writel(cntl, &i2c_base->ic_con); in __dw_i2c_set_bus_speed()
|
| /external/u-boot/drivers/serial/ |
| D | serial_bcm283x_mu.c | 37 u32 cntl; member
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 2612 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2614 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2615 [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>,
2618 (ins x86memop:$src1, immtype:$cntl),
2620 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2621 [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>,
2691 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
2692 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
2693 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>,
2696 def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl),
[all …]
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_uvd.c | 92 unsigned cntl; member
1346 set_reg(dec, dec->reg.cntl, 1); in ruvd_end_frame()
1483 dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15; in si_common_uvd_create_decoder()
1488 dec->reg.cntl = RUVD_ENGINE_CNTL; in si_common_uvd_create_decoder()
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_state.c | 208 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & in r200_set_blend_state() local
221 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE; in r200_set_blend_state()
226 … rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE; in r200_set_blend_state()
229 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl; in r200_set_blend_state()
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| D | radeon_uvd.c | 98 unsigned cntl; member
1260 set_reg(dec, dec->reg.cntl, 1); in ruvd_end_frame()
1377 dec->reg.cntl = RUVD_ENGINE_CNTL; in ruvd_create_decoder()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 2354 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2356 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2357 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2360 (ins x86memop:$src1, immtype:$cntl),
2362 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2363 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenGlobalISel.inc | 10507 … }:$src1, (imm:{ *:[i32] }):$cntl) => (LWPVAL32rri GR32:{ *:[i32] }:$src0, GR32:{ *:[i32] }:$src…
10511 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cntl
10531 … }:$src1, (imm:{ *:[i32] }):$cntl) => (LWPVAL64rri GR64:{ *:[i64] }:$src0, GR32:{ *:[i32] }:$src…
10535 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cntl
|