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Searched refs:coerce (Results 1 – 25 of 176) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Ddsp-patterns-cmp-vselect.ll7 define { i32 } @select_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
9 %0 = bitcast i32 %a0.coerce to <2 x i16>
10 %1 = bitcast i32 %a1.coerce to <2 x i16>
11 %2 = bitcast i32 %a2.coerce to <2 x i16>
12 %3 = bitcast i32 %a3.coerce to <2 x i16>
24 define { i32 } @select_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
26 %0 = bitcast i32 %a0.coerce to <2 x i16>
27 %1 = bitcast i32 %a1.coerce to <2 x i16>
28 %2 = bitcast i32 %a2.coerce to <2 x i16>
29 %3 = bitcast i32 %a3.coerce to <2 x i16>
[all …]
Ddsp-r2.ll3 define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nou…
7 %1 = bitcast i32 %a1.coerce to <2 x i16>
8 %2 = bitcast i32 %a2.coerce to <2 x i16>
15 define i64 @test__builtin_mips_dps_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nou…
19 %1 = bitcast i32 %a1.coerce to <2 x i16>
20 %2 = bitcast i32 %a2.coerce to <2 x i16>
27 define i64 @test__builtin_mips_mulsa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
31 %1 = bitcast i32 %a1.coerce to <2 x i16>
32 %2 = bitcast i32 %a2.coerce to <2 x i16>
39 define i64 @test__builtin_mips_dpax_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) no…
[all …]
Ddsp-r1.ll112 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
116 %1 = bitcast i32 %a1.coerce to <4 x i8>
117 %2 = bitcast i32 %a2.coerce to <4 x i8>
124 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
128 %1 = bitcast i32 %a1.coerce to <4 x i8>
129 %2 = bitcast i32 %a2.coerce to <4 x i8>
136 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
140 %1 = bitcast i32 %a1.coerce to <4 x i8>
141 %2 = bitcast i32 %a2.coerce to <4 x i8>
148 define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
[all …]
Ddsp-patterns.ll37 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
39 %0 = bitcast i32 %a.coerce to <2 x i16>
40 %1 = bitcast i32 %b.coerce to <2 x i16>
50 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
52 %0 = bitcast i32 %a.coerce to <2 x i16>
53 %1 = bitcast i32 %b.coerce to <2 x i16>
68 define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) {
70 %0 = bitcast i32 %a.coerce to <2 x i16>
71 %1 = bitcast i32 %b.coerce to <2 x i16>
81 define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
[all …]
/external/llvm/test/CodeGen/Mips/
Ddsp-patterns-cmp-vselect.ll7 define { i32 } @select_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
9 %0 = bitcast i32 %a0.coerce to <2 x i16>
10 %1 = bitcast i32 %a1.coerce to <2 x i16>
11 %2 = bitcast i32 %a2.coerce to <2 x i16>
12 %3 = bitcast i32 %a3.coerce to <2 x i16>
24 define { i32 } @select_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
26 %0 = bitcast i32 %a0.coerce to <2 x i16>
27 %1 = bitcast i32 %a1.coerce to <2 x i16>
28 %2 = bitcast i32 %a2.coerce to <2 x i16>
29 %3 = bitcast i32 %a3.coerce to <2 x i16>
[all …]
Ddsp-r2.ll3 define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nou…
7 %1 = bitcast i32 %a1.coerce to <2 x i16>
8 %2 = bitcast i32 %a2.coerce to <2 x i16>
15 define i64 @test__builtin_mips_dps_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nou…
19 %1 = bitcast i32 %a1.coerce to <2 x i16>
20 %2 = bitcast i32 %a2.coerce to <2 x i16>
27 define i64 @test__builtin_mips_mulsa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
31 %1 = bitcast i32 %a1.coerce to <2 x i16>
32 %2 = bitcast i32 %a2.coerce to <2 x i16>
39 define i64 @test__builtin_mips_dpax_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) no…
[all …]
Ddsp-r1.ll112 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
116 %1 = bitcast i32 %a1.coerce to <4 x i8>
117 %2 = bitcast i32 %a2.coerce to <4 x i8>
124 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
128 %1 = bitcast i32 %a1.coerce to <4 x i8>
129 %2 = bitcast i32 %a2.coerce to <4 x i8>
136 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
140 %1 = bitcast i32 %a1.coerce to <4 x i8>
141 %2 = bitcast i32 %a2.coerce to <4 x i8>
148 define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n…
[all …]
Ddsp-patterns.ll37 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
39 %0 = bitcast i32 %a.coerce to <2 x i16>
40 %1 = bitcast i32 %b.coerce to <2 x i16>
50 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
52 %0 = bitcast i32 %a.coerce to <2 x i16>
53 %1 = bitcast i32 %b.coerce to <2 x i16>
68 define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) {
70 %0 = bitcast i32 %a.coerce to <2 x i16>
71 %1 = bitcast i32 %b.coerce to <2 x i16>
81 define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
[all …]
/external/llvm/test/Transforms/LoopRotate/
Dnosimplifylatch.ll9 …St3__14findINS_11__wrap_iterIPiEEiEET_S4_S4_RKT0_(i64 %__first.coerce, i64 %__last.coerce, i32* no…
11 %coerce.val.ip = inttoptr i64 %__first.coerce to i32*
12 %coerce.val.ip2 = inttoptr i64 %__last.coerce to i32*
16 %coerce.val.ip9 = phi i32* [ %incdec.ptr.i, %for.inc ], [ %coerce.val.ip, %entry ]
17 %lnot.i = icmp eq i32* %coerce.val.ip9, %coerce.val.ip2
21 %0 = load i32, i32* %coerce.val.ip9, align 4
27 %incdec.ptr.i = getelementptr inbounds i32, i32* %coerce.val.ip9, i64 1
31 %coerce.val.ip9.lcssa = phi i32* [ %coerce.val.ip9, %for.cond ], [ %coerce.val.ip9, %for.body ]
32 %coerce.val.pi = ptrtoint i32* %coerce.val.ip9.lcssa to i64
33 ret i64 %coerce.val.pi
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopRotate/
Dnosimplifylatch.ll9 …St3__14findINS_11__wrap_iterIPiEEiEET_S4_S4_RKT0_(i64 %__first.coerce, i64 %__last.coerce, i32* no…
11 %coerce.val.ip = inttoptr i64 %__first.coerce to i32*
12 %coerce.val.ip2 = inttoptr i64 %__last.coerce to i32*
16 %coerce.val.ip9 = phi i32* [ %incdec.ptr.i, %for.inc ], [ %coerce.val.ip, %entry ]
17 %lnot.i = icmp eq i32* %coerce.val.ip9, %coerce.val.ip2
21 %0 = load i32, i32* %coerce.val.ip9, align 4
27 %incdec.ptr.i = getelementptr inbounds i32, i32* %coerce.val.ip9, i64 1
31 %coerce.val.ip9.lcssa = phi i32* [ %coerce.val.ip9, %for.cond ], [ %coerce.val.ip9, %for.body ]
32 %coerce.val.pi = ptrtoint i32* %coerce.val.ip9.lcssa to i64
33 ret i64 %coerce.val.pi
/external/llvm/test/Transforms/SLPVectorizer/ARM/
Dsroa.ll15 …Aed(%class.Complex* noalias nocapture sret %agg.result, [4 x i32] %a.coerce, [4 x i32] %b.coerce) {
17 %a.coerce.fca.0.extract = extractvalue [4 x i32] %a.coerce, 0
18 %a.sroa.0.0.insert.ext = zext i32 %a.coerce.fca.0.extract to i64
19 %a.coerce.fca.1.extract = extractvalue [4 x i32] %a.coerce, 1
20 %a.sroa.0.4.insert.ext = zext i32 %a.coerce.fca.1.extract to i64
24 %a.coerce.fca.2.extract = extractvalue [4 x i32] %a.coerce, 2
25 %a.sroa.3.8.insert.ext = zext i32 %a.coerce.fca.2.extract to i64
26 %a.coerce.fca.3.extract = extractvalue [4 x i32] %a.coerce, 3
27 %a.sroa.3.12.insert.ext = zext i32 %a.coerce.fca.3.extract to i64
31 %b.coerce.fca.0.extract = extractvalue [4 x i32] %b.coerce, 0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/ARM/
Dsroa.ll15 …Aed(%class.Complex* noalias nocapture sret %agg.result, [4 x i32] %a.coerce, [4 x i32] %b.coerce) {
17 %a.coerce.fca.0.extract = extractvalue [4 x i32] %a.coerce, 0
18 %a.sroa.0.0.insert.ext = zext i32 %a.coerce.fca.0.extract to i64
19 %a.coerce.fca.1.extract = extractvalue [4 x i32] %a.coerce, 1
20 %a.sroa.0.4.insert.ext = zext i32 %a.coerce.fca.1.extract to i64
24 %a.coerce.fca.2.extract = extractvalue [4 x i32] %a.coerce, 2
25 %a.sroa.3.8.insert.ext = zext i32 %a.coerce.fca.2.extract to i64
26 %a.coerce.fca.3.extract = extractvalue [4 x i32] %a.coerce, 3
27 %a.sroa.3.12.insert.ext = zext i32 %a.coerce.fca.3.extract to i64
31 %b.coerce.fca.0.extract = extractvalue [4 x i32] %b.coerce, 0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Df128-aggregates.ll51 define fp128 @testStruct_01(fp128 inreg returned %a.coerce) {
60 ret fp128 %a.coerce
64 define fp128 @testStruct_02([8 x fp128] %a.coerce) {
74 %a.coerce.fca.7.extract = extractvalue [8 x fp128] %a.coerce, 7
75 ret fp128 %a.coerce.fca.7.extract
116 define fp128 @testStruct_04([8 x fp128] %a.coerce) {
126 %a.coerce.fca.3.extract = extractvalue [8 x fp128] %a.coerce, 3
127 ret fp128 %a.coerce.fca.3.extract
131 define fp128 @testHUnion_01([1 x fp128] %a.coerce) {
140 %a.coerce.fca.0.extract = extractvalue [1 x fp128] %a.coerce, 0
[all …]
Dvarargs-struct-float.ll8 define void @foo(float inreg %s.coerce) nounwind {
11 %coerce.dive = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0
12 store float %s.coerce, float* %coerce.dive, align 1
13 %coerce.dive1 = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0
14 %0 = load float, float* %coerce.dive1, align 1
Daddi-offset-fold.ll8 define signext i32 @foo([2 x i64] %a.coerce) local_unnamed_addr #0 {
11 %a.coerce.fca.0.extract = extractvalue [2 x i64] %a.coerce, 0
12 %a.coerce.fca.1.extract = extractvalue [2 x i64] %a.coerce, 1
14 store i64 %a.coerce.fca.0.extract, i64* %a.0.a.0..sroa_cast, align 8
15 %tmp.sroa.2.0.extract.trunc = trunc i64 %a.coerce.fca.1.extract to i8
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/EarlyCSE/AArch64/
Dintrinsics.ll6 define <4 x i32> @test_cse(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
11 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
12 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
23 %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
24 %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
40 define <4 x i32> @test_cse2(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
45 …all void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %s.coerce.fca.0.extract, <4 x i32> %s.coerce.…
46 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
47 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
58 %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
[all …]
/external/llvm/test/Transforms/EarlyCSE/AArch64/
Dintrinsics.ll4 define <4 x i32> @test_cse(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
9 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
10 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
21 %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
22 %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
38 define <4 x i32> @test_cse2(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
44 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
45 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
56 %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
57 %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dirtranslator-duplicate-types-param.ll9 define i64 @param_two_struct([2 x i64] %t.coerce, [2 x i64] %s.coerce) {
11 %t.coerce.fca.0.extract = extractvalue [2 x i64] %t.coerce, 0
12 %s.coerce.fca.1.extract = extractvalue [2 x i64] %s.coerce, 1
13 %add = add nsw i64 %s.coerce.fca.1.extract, %t.coerce.fca.0.extract
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfp16-instructions.ll32 ; that for the time being by passing "float %f.coerce" and the necessary
36 define float @RetValBug(float %A.coerce) {
49 define float @Add(float %a.coerce, float %b.coerce) {
51 %0 = bitcast float %a.coerce to i32
54 %2 = bitcast float %b.coerce to i32
105 define zeroext i1 @VCMP1(float %F.coerce, float %G.coerce) {
107 %0 = bitcast float %F.coerce to i32
110 %2 = bitcast float %G.coerce to i32
138 define zeroext i1 @VCMP2(float %F.coerce) {
140 %0 = bitcast float %F.coerce to i32
[all …]
/external/llvm/test/Transforms/InstCombine/
Dvector-type.ll6 define i32 @vselect1(i32 %a.coerce, i32 %b.coerce, i32 %c.coerce) {
8 %0 = bitcast i32 %a.coerce to <2 x i16>
9 %1 = bitcast i32 %b.coerce to <2 x i16>
10 %2 = bitcast i32 %c.coerce to <2 x i16>
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dvector-type.ll6 define i32 @vselect1(i32 %a.coerce, i32 %b.coerce, i32 %c.coerce) {
8 %0 = bitcast i32 %a.coerce to <2 x i16>
9 %1 = bitcast i32 %b.coerce to <2 x i16>
10 %2 = bitcast i32 %c.coerce to <2 x i16>
/external/llvm/test/CodeGen/PowerPC/
Dvarargs-struct-float.ll8 define void @foo(float inreg %s.coerce) nounwind {
11 %coerce.dive = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0
12 store float %s.coerce, float* %coerce.dive, align 1
13 %coerce.dive1 = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0
14 %0 = load float, float* %coerce.dive1, align 1
/external/llvm/test/CodeGen/Mips/cconv/
Darguments-varargs-small-structs-byte.ll170 %.coerce = alloca { i24 }
173 %1 = bitcast { i24 }* %.coerce to i8*
176 %3 = getelementptr { i24 }, { i24 }* %.coerce, i32 0, i32 0
203 %.coerce = alloca { i40 }
206 %1 = bitcast { i40 }* %.coerce to i8*
209 %3 = getelementptr { i40 }, { i40 }* %.coerce, i32 0, i32 0
220 %.coerce = alloca { i48 }
223 %1 = bitcast { i48 }* %.coerce to i8*
226 %3 = getelementptr { i48 }, { i48 }* %.coerce, i32 0, i32 0
237 %.coerce = alloca { i56 }
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/X86/
Dsplit-dwarf-cross-unit-reference.ll110 define void @_Z3foo2t1(i32 %t.coerce) #3 !dbg !20 {
116 %coerce.dive = getelementptr inbounds %struct.t1, %struct.t1* %t, i32 0, i32 0
117 store i32 %t.coerce, i32* %coerce.dive, align 4
122 %coerce.dive1 = getelementptr inbounds %struct.t1, %struct.t1* %agg.tmp, i32 0, i32 0, !dbg !26
123 %2 = load i32, i32* %coerce.dive1, align 4, !dbg !26
124 %coerce.dive.i = getelementptr inbounds %struct.t1, %struct.t1* %t.i, i32 0, i32 0
125 store i32 %2, i32* %coerce.dive.i, align 4
134 define void @_Z3bar2t1(i32 %t.coerce) #3 !dbg !29 {
140 %coerce.dive = getelementptr inbounds %struct.t1, %struct.t1* %t, i32 0, i32 0
141 store i32 %t.coerce, i32* %coerce.dive, align 4
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/
Darguments-varargs-small-structs-byte.ll170 %.coerce = alloca { i24 }
173 %1 = bitcast { i24 }* %.coerce to i8*
176 %3 = getelementptr { i24 }, { i24 }* %.coerce, i32 0, i32 0
203 %.coerce = alloca { i40 }
206 %1 = bitcast { i40 }* %.coerce to i8*
209 %3 = getelementptr { i40 }, { i40 }* %.coerce, i32 0, i32 0
220 %.coerce = alloca { i48 }
223 %1 = bitcast { i48 }* %.coerce to i8*
226 %3 = getelementptr { i48 }, { i48 }* %.coerce, i32 0, i32 0
237 %.coerce = alloca { i56 }
[all …]

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