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Searched refs:confr (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/drivers/spi/
Dzynq_spi.c98 u32 confr; in zynq_spi_init_hw() local
101 confr = ZYNQ_SPI_ENR_SPI_EN_MASK; in zynq_spi_init_hw()
102 writel(~confr, &regs->enr); in zynq_spi_init_hw()
116 confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | in zynq_spi_init_hw()
118 confr &= ~ZYNQ_SPI_CR_MSA_MASK; in zynq_spi_init_hw()
119 writel(confr, &regs->cr); in zynq_spi_init_hw()
200 u32 confr; in zynq_spi_release_bus() local
202 confr = ZYNQ_SPI_ENR_SPI_EN_MASK; in zynq_spi_release_bus()
203 writel(~confr, &regs->enr); in zynq_spi_release_bus()
279 uint32_t confr; in zynq_spi_set_speed() local
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Dzynq_qspi.c122 u32 confr; in zynq_qspi_init_hw() local
142 confr = readl(&regs->cr); in zynq_qspi_init_hw()
143 confr &= ~ZYNQ_QSPI_CR_MSA_MASK; in zynq_qspi_init_hw()
144 confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK | in zynq_qspi_init_hw()
147 writel(confr, &regs->cr); in zynq_qspi_init_hw()
150 confr = readl(&regs->lqspicfg); in zynq_qspi_init_hw()
151 confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; in zynq_qspi_init_hw()
152 writel(confr, &regs->lqspicfg); in zynq_qspi_init_hw()
268 u32 confr; in zynq_qspi_chipselect() local
271 confr = readl(&regs->cr); in zynq_qspi_chipselect()
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Domap3_spi.c357 uint32_t confr, div = 0; in _omap3_spi_set_speed() local
359 confr = readl(&priv->regs->channel[priv->cs].chconf); in _omap3_spi_set_speed()
371 confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK; in _omap3_spi_set_speed()
372 confr |= div << 2; in _omap3_spi_set_speed()
374 omap3_spi_write_chconf(priv, confr); in _omap3_spi_set_speed()
379 uint32_t confr; in _omap3_spi_set_mode() local
381 confr = readl(&priv->regs->channel[priv->cs].chconf); in _omap3_spi_set_mode()
387 confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1); in _omap3_spi_set_mode()
388 confr |= OMAP3_MCSPI_CHCONF_DPE0; in _omap3_spi_set_mode()
390 confr &= ~OMAP3_MCSPI_CHCONF_DPE0; in _omap3_spi_set_mode()
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