| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | testComparesllleull.ll | 14 %conv1 = zext i1 %cmp to i64
15 ret i64 %conv1
27 %conv1 = sext i1 %cmp to i64
28 ret i64 %conv1
40 %conv1 = zext i1 %cmp to i64
41 ret i64 %conv1
52 %conv1 = sext i1 %cmp to i64
53 ret i64 %conv1
64 %conv1 = zext i1 %cmp to i64
65 store i64 %conv1, i64* @glob
[all …]
|
| D | testComparesllgeull.ll | 14 %conv1 = zext i1 %cmp to i64
15 ret i64 %conv1
27 %conv1 = sext i1 %cmp to i64
28 ret i64 %conv1
40 %conv1 = zext i1 %cmp to i64
41 ret i64 %conv1
51 %conv1 = sext i1 %cmp to i64
52 ret i64 %conv1
62 %conv1 = zext i1 %cmp to i64
63 store i64 %conv1, i64* @glob
[all …]
|
| D | testComparesllgtsll.ll | 22 %conv1 = zext i1 %cmp to i64
23 ret i64 %conv1
39 %conv1 = sext i1 %cmp to i64
40 ret i64 %conv1
54 %conv1 = zext i1 %cmp to i64
55 ret i64 %conv1
66 %conv1 = sext i1 %cmp to i64
67 ret i64 %conv1
82 %conv1 = zext i1 %cmp to i64
83 store i64 %conv1, i64* @glob, align 8
[all …]
|
| D | testCompareslleqsll.ll | 21 %conv1 = zext i1 %cmp to i64
22 ret i64 %conv1
35 %conv1 = sext i1 %cmp to i64
36 ret i64 %conv1
48 %conv1 = zext i1 %cmp to i64
49 ret i64 %conv1
61 %conv1 = sext i1 %cmp to i64
62 ret i64 %conv1
78 %conv1 = zext i1 %cmp to i64
79 store i64 %conv1, i64* @glob, align 8
[all …]
|
| D | testComparesllequll.ll | 21 %conv1 = zext i1 %cmp to i64
22 ret i64 %conv1
35 %conv1 = sext i1 %cmp to i64
36 ret i64 %conv1
48 %conv1 = zext i1 %cmp to i64
49 ret i64 %conv1
61 %conv1 = sext i1 %cmp to i64
62 ret i64 %conv1
78 %conv1 = zext i1 %cmp to i64
79 store i64 %conv1, i64* @glob, align 8
[all …]
|
| D | testComparesllgesll.ll | 20 %conv1 = zext i1 %cmp to i64
21 ret i64 %conv1
35 %conv1 = sext i1 %cmp to i64
36 ret i64 %conv1
47 %conv1 = zext i1 %cmp to i64
48 ret i64 %conv1
59 %conv1 = sext i1 %cmp to i64
60 ret i64 %conv1
74 %conv1 = zext i1 %cmp to i64
75 store i64 %conv1, i64* @glob, align 8
[all …]
|
| D | testComparesllneull.ll | 20 %conv1 = zext i1 %cmp to i64
21 ret i64 %conv1
33 %conv1 = sext i1 %cmp to i64
34 ret i64 %conv1
45 %conv1 = zext i1 %cmp to i64
46 ret i64 %conv1
57 %conv1 = sext i1 %cmp to i64
58 ret i64 %conv1
73 %conv1 = zext i1 %cmp to i64
74 store i64 %conv1, i64* @glob, align 8
[all …]
|
| D | testComparesllnesll.ll | 20 %conv1 = zext i1 %cmp to i64
21 ret i64 %conv1
33 %conv1 = sext i1 %cmp to i64
34 ret i64 %conv1
45 %conv1 = zext i1 %cmp to i64
46 ret i64 %conv1
57 %conv1 = sext i1 %cmp to i64
58 ret i64 %conv1
73 %conv1 = zext i1 %cmp to i64
74 store i64 %conv1, i64* @glob, align 8
[all …]
|
| D | ctrloop-i64.ll | 12 %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
16 %conv1 = add i64 %conv, %0
22 ret i64 %conv1
34 %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
38 %conv1 = add i64 %conv, %0
44 ret i64 %conv1
56 %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
60 %conv1 = add i64 %conv, %0
66 ret i64 %conv1
78 %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
[all …]
|
| D | testCompareslllesll.ll | 21 %conv1 = zext i1 %cmp to i64
22 ret i64 %conv1
37 %conv1 = sext i1 %cmp to i64
38 ret i64 %conv1
51 %conv1 = zext i1 %cmp to i64
52 ret i64 %conv1
65 %conv1 = sext i1 %cmp to i64
66 ret i64 %conv1
83 %conv1 = zext i1 %cmp to i64
84 store i64 %conv1, i64* @glob, align 8
[all …]
|
| D | ppcf128sf.ll | 94 %conv1 = trunc i32 %conv to i8
95 store i8 %conv1, i8* @var, align 1
107 %conv1 = trunc i32 %conv to i8
108 store i8 %conv1, i8* @var, align 1
120 %conv1 = trunc i32 %conv to i8
121 store i8 %conv1, i8* @var, align 1
133 %conv1 = trunc i32 %conv to i8
134 store i8 %conv1, i8* @var, align 1
146 %conv1 = trunc i32 %conv to i8
147 store i8 %conv1, i8* @var, align 1
[all …]
|
| D | fp-to-int-ext.ll | 10 %conv1 = sitofp i64 %conv to double
11 ret double %conv1
23 %conv1 = sitofp i64 %conv to double
24 ret double %conv1
37 %conv1 = sitofp i64 %conv to double
38 ret double %conv1
55 %conv1 = sitofp i64 %conv to double
56 ret double %conv1
|
| D | fp-to-int-to-fp.ll | 10 %conv1 = sitofp i64 %conv to float
11 ret float %conv1
28 %conv1 = sitofp i64 %conv to double
29 ret double %conv1
45 %conv1 = uitofp i64 %conv to float
46 ret float %conv1
57 %conv1 = uitofp i64 %conv to double
58 ret double %conv1
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | double-float-shrink-1.ll | 15 %conv1 = fptrunc double %call to float
16 ret float %conv1
32 %conv1 = fptrunc double %call to float
33 ret float %conv1
49 %conv1 = fptrunc double %call to float
50 ret float %conv1
66 %conv1 = fptrunc double %call to float
67 ret float %conv1
83 %conv1 = fptrunc double %call to float
84 ret float %conv1
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | dsp-mlal.ll | 15 %conv1 = sext i32 %Xn1 to i64
16 %mul = mul nsw i64 %conv1, %conv
36 %conv1 = sext i32 %b to i64
37 %mul = mul nsw i64 %conv1, %conv
51 %conv1 = sext i32 %b to i64
52 %mul = mul nsw i64 %conv1, %conv
66 %conv1 = sext i32 %b to i64
68 %mul = mul nsw i64 %conv2, %conv1
83 %conv1 = sext i32 %c to i64
84 %mul = mul nsw i64 %conv1, %conv
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | longMAC.ll | 11 %conv1 = zext i32 %b to i64
12 %mul = mul i64 %conv1, %conv
21 %conv1 = sext i32 %b to i64
22 %mul = mul nsw i64 %conv1, %conv
31 %conv1 = zext i32 %a to i64
32 %mul = mul i64 %conv, %conv1
42 %conv1 = sext i32 %a to i64
43 %mul = mul nsw i64 %conv, %conv1
73 %conv1 = zext i32 %b to i64
84 %conv1 = sext i32 %b to i64
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | ctrloop-i64.ll | 12 %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
16 %conv1 = add i64 %conv, %0
22 ret i64 %conv1
34 %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
38 %conv1 = add i64 %conv, %0
44 ret i64 %conv1
56 %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
60 %conv1 = add i64 %conv, %0
66 ret i64 %conv1
78 %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
[all …]
|
| D | ppcf128sf.ll | 94 %conv1 = trunc i32 %conv to i8
95 store i8 %conv1, i8* @var, align 1
107 %conv1 = trunc i32 %conv to i8
108 store i8 %conv1, i8* @var, align 1
120 %conv1 = trunc i32 %conv to i8
121 store i8 %conv1, i8* @var, align 1
133 %conv1 = trunc i32 %conv to i8
134 store i8 %conv1, i8* @var, align 1
146 %conv1 = trunc i32 %conv to i8
147 store i8 %conv1, i8* @var, align 1
[all …]
|
| D | fp-to-int-ext.ll | 10 %conv1 = sitofp i64 %conv to double
11 ret double %conv1
23 %conv1 = sitofp i64 %conv to double
24 ret double %conv1
37 %conv1 = sitofp i64 %conv to double
38 ret double %conv1
55 %conv1 = sitofp i64 %conv to double
56 ret double %conv1
|
| D | fp-to-int-to-fp.ll | 10 %conv1 = sitofp i64 %conv to float
11 ret float %conv1
29 %conv1 = sitofp i64 %conv to double
30 ret double %conv1
47 %conv1 = uitofp i64 %conv to float
48 ret float %conv1
60 %conv1 = uitofp i64 %conv to double
61 ret double %conv1
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | longMACt.ll | 8 %conv1 = zext i32 %b to i64
9 %mul = mul i64 %conv1, %conv
18 %conv1 = sext i32 %b to i64
19 %mul = mul nsw i64 %conv1, %conv
28 %conv1 = zext i32 %a to i64
29 %mul = mul i64 %conv, %conv1
39 %conv1 = sext i32 %a to i64
40 %mul = mul nsw i64 %conv, %conv1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/ |
| D | longMACt.ll | 8 %conv1 = zext i32 %b to i64
9 %mul = mul i64 %conv1, %conv
18 %conv1 = sext i32 %b to i64
19 %mul = mul nsw i64 %conv1, %conv
28 %conv1 = zext i32 %a to i64
29 %mul = mul i64 %conv, %conv1
39 %conv1 = sext i32 %a to i64
40 %mul = mul nsw i64 %conv, %conv1
|
| /external/llvm/test/CodeGen/NVPTX/ |
| D | sext-in-reg.ll | 11 %conv1 = ashr exact i64 %sext, 56
16 %add = add nsw i64 %conv4, %conv1
29 %conv1 = ashr exact i64 %sext, 32
34 %add = add nsw i64 %conv4, %conv1
47 %conv1 = ashr exact i64 %sext, 48
52 %add = add nsw i64 %conv4, %conv1
65 %conv1 = ashr exact i32 %sext, 24
70 %add = add nsw i32 %conv4, %conv1
83 %conv1 = ashr exact i32 %sext, 16
88 %add = add nsw i32 %conv4, %conv1
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/ |
| D | sext-in-reg.ll | 11 %conv1 = ashr exact i64 %sext, 56
16 %add = add nsw i64 %conv4, %conv1
29 %conv1 = ashr exact i64 %sext, 32
34 %add = add nsw i64 %conv4, %conv1
47 %conv1 = ashr exact i64 %sext, 48
52 %add = add nsw i64 %conv4, %conv1
65 %conv1 = ashr exact i32 %sext, 24
70 %add = add nsw i32 %conv4, %conv1
83 %conv1 = ashr exact i32 %sext, 16
88 %add = add nsw i32 %conv4, %conv1
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | memops.ll | 11 %conv1 = trunc i32 %add to i8
12 store i8 %conv1, i8* %p, align 1
22 %conv1 = zext i8 %0 to i32
23 %add = add nsw i32 %conv1, %conv
35 %conv1 = zext i8 %0 to i32
36 %sub = sub nsw i32 %conv1, %conv
69 %conv1 = trunc i32 %and to i8
70 store i8 %conv1, i8* %p, align 1
81 %conv1 = trunc i32 %or to i8
82 store i8 %conv1, i8* %p, align 1
[all …]
|