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Searched refs:createRegOperand (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp179 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { in createRegOperand() function in AMDGPUDisassembler
184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() function in AMDGPUDisassembler
190 return createRegOperand(RegCl.getRegister(Val)); in createRegOperand()
226 return createRegOperand(SRegClassID, Val >> shift); in createSRegOperand()
238 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); in decodeOperand_VGPR_32()
242 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); in decodeOperand_VReg_64()
246 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); in decodeOperand_VReg_96()
250 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); in decodeOperand_VReg_128()
364 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); in decodeSrcOp()
392 case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI)); in decodeSpecialReg32()
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DAMDGPUDisassembler.h46 MCOperand createRegOperand(unsigned int RegId) const;
47 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp278 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), in convertSDWAInst()
390 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { in createRegOperand() function in AMDGPUDisassembler
395 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() function in AMDGPUDisassembler
401 return createRegOperand(RegCl.getRegister(Val)); in createRegOperand()
441 return createRegOperand(SRegClassID, Val >> shift); in createSRegOperand()
470 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); in decodeOperand_VGPR_32()
474 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); in decodeOperand_VReg_64()
478 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); in decodeOperand_VReg_96()
482 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); in decodeOperand_VReg_128()
706 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); in decodeSrcOp()
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DAMDGPUDisassembler.h62 MCOperand createRegOperand(unsigned int RegId) const;
63 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;