Searched refs:crlapb_base (Results 1 – 4 of 4) sorted by relevance
97 tmp = readl(&crlapb_base->rst_lpd_top); in set_r5_reset()104 writel(tmp, &crlapb_base->rst_lpd_top); in set_r5_reset()111 tmp = readl(&crlapb_base->rst_lpd_top); in release_r5_reset()118 writel(tmp, &crlapb_base->rst_lpd_top); in release_r5_reset()125 tmp = readl(&crlapb_base->cpu_r5_ctrl); in enable_clock_r5()127 writel(tmp, &crlapb_base->cpu_r5_ctrl); in enable_clock_r5()158 u32 val = readl(&crlapb_base->rst_lpd_top); in cpu_status()
40 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()44 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()72 &crlapb_base->boot_mode); in spl_boot_device()75 reg = readl(&crlapb_base->boot_mode); in spl_boot_device()
355 val = readl(&crlapb_base->timestamp_ref_ctrl); in board_early_init_r()359 val = readl(&crlapb_base->timestamp_ref_ctrl); in board_early_init_r()361 writel(val, &crlapb_base->timestamp_ref_ctrl); in board_early_init_r()473 ret = readl(&crlapb_base->reset_reason); in reset_reason()489 writel(~0, &crlapb_base->reset_reason); in reset_reason()512 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®); in board_late_init()
57 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) macro