Home
last modified time | relevance | path

Searched refs:crn (Results 1 – 17 of 17) sorted by relevance

/external/kernel-headers/original/uapi/linux/
Dvirtio_scsi.h49 __u8 crn; member
59 __u8 crn; member
/external/kernel-headers/original/uapi/asm-arm64/asm/
Dkvm.h203 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
207 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
/external/kernel-headers/original/uapi/asm-arm/asm/
Dkvm.h165 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument
168 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td21 class AT<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
30 let Encoding{10-7} = crn;
80 class DC<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
89 let Encoding{10-7} = crn;
107 class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2,
115 let Encoding{10-7} = crn;
216 class TLBI<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
225 let Encoding{10-7} = crn;
269 class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
278 let Encoding{10-7} = crn;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td21 class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm,
29 let Encoding{10-7} = crn;
82 class DC<string name, bits<3> op1, bits<4> crn, bits<4> crm,
90 let Encoding{10-7} = crn;
112 class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2,
120 let Encoding{10-7} = crn;
321 class TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm,
329 let Encoding{10-7} = crn;
427 class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
436 let Encoding{10-7} = crn;
[all …]
/external/v8/src/arm/
Dassembler-arm.h964 CRegister crd, CRegister crn, CRegister crm,
968 CRegister crd, CRegister crn, CRegister crm,
972 Register rd, CRegister crn, CRegister crm,
976 Register rd, CRegister crn, CRegister crm,
980 Register rd, CRegister crn, CRegister crm,
984 Register rd, CRegister crn, CRegister crm,
Dassembler-arm.cc2399 CRegister crn, in cdp() argument
2404 emit(cond | B27 | B26 | B25 | (opcode_1 & 15)*B20 | crn.code()*B16 | in cdp()
2409 CRegister crn, CRegister crm, int opcode_2) { in cdp2() argument
2410 cdp(coproc, opcode_1, crd, crn, crm, opcode_2, kSpecialCondition); in cdp2()
2417 CRegister crn, in mcr() argument
2422 emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | crn.code()*B16 | in mcr()
2427 CRegister crn, CRegister crm, int opcode_2) { in mcr2() argument
2428 mcr(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition); in mcr2()
2435 CRegister crn, in mrc() argument
2440 emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | L | crn.code()*B16 | in mrc()
[all …]
Ddisasm-arm.cc1669 int crn = instr->Bits(19, 16); in DecodeTypeCP15() local
1673 if ((opc1 == 0) && (crn == 7)) { in DecodeTypeCP15()
Dsimulator-arm.cc3524 int crn = instr->Bits(19, 16); in DecodeTypeCP15() local
3528 if ((opc1 == 0) && (crn == 7)) { in DecodeTypeCP15()
/external/vixl/src/aarch64/
Dconstants-aarch64.h349 template<int op0, int op1, int crn, int crm, int op2>
355 (crn << CRn_offset) |
368 template<int op1, int crn, int crm, int op2>
373 (crn << CRn_offset) |
Dmacro-assembler-aarch64.h1991 void Sys(int op1, int crn, int crm, int op2, const Register& rt = xzr) {
1994 sys(op1, crn, crm, op2, rt);
Dassembler-aarch64.cc1755 void Assembler::sys(int op1, int crn, int crm, int op2, const Register& xt) { in sys() argument
1757 Emit(SYS | ImmSysOp1(op1) | CRn(crn) | CRm(crm) | ImmSysOp2(op2) | Rt(xt)); in sys()
Dassembler-aarch64.h2109 void sys(int op1, int crn, int crm, int op2, const Register& xt = xzr);
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md1260 System instruction with pre-encoded op (op1:crn:crm:op2).
1269 void sys(int op1, int crn, int crm, int op2, const Register& xt = xzr)
/external/cldr/tools/java/org/unicode/cldr/util/data/
Diso-639-3_Name_Index.tab1438 crn El Nayar Cora Cora, El Nayar
Diso-639-3.tab1388 crn I L El Nayar Cora
Dlanguage-subtag-registry8417 Subtag: crn