/external/llvm/test/CodeGen/AArch64/ |
D | fp16-v4-instructions.ll | 280 ; CHECK-DAG: csetm {{.*}}, ne 281 ; CHECK-DAG: csetm {{.*}}, ne 282 ; CHECK-DAG: csetm {{.*}}, ne 283 ; CHECK-DAG: csetm {{.*}}, ne 299 ; CHECK-DAG: csetm [[REG1:w[0-9]+]], eq 300 ; CHECK-DAG: csetm [[REG2:w[0-9]+]], eq 301 ; CHECK-DAG: csetm [[REG3:w[0-9]+]], eq 302 ; CHECK-DAG: csetm [[REG4:w[0-9]+]], eq 322 ; CHECK-DAG: csetm {{.*}}, hi 323 ; CHECK-DAG: csetm {{.*}}, hi [all …]
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D | cond-sel.ll | 145 ; CHECK: csetm {{w[0-9]+}}, ls 234 ; CHECK: csetm {{w[0-9]+}}, eq 240 ; CHECK: csetm {{x[0-9]+}}, ls
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D | arm64-neon-select_cc.ll | 215 ; CHECK: csetm [[MASK:w[0-9]+]], ne
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | fp16-v4-instructions.ll | 308 ; CHECK-FP16: csetm {{.*}}, ne 310 ; CHECK-FP16: csetm {{.*}}, ne 312 ; CHECK-FP16: csetm {{.*}}, ne 314 ; CHECK-FP16: csetm {{.*}}, ne 334 ; CHECK-FP16: csetm {{.*}}, eq 336 ; CHECK-FP16: csetm {{.*}}, eq 338 ; CHECK-FP16: csetm {{.*}}, eq 340 ; CHECK-FP16: csetm {{.*}}, eq 358 ; CHECK-FP16: csetm {{.*}}, hi 360 ; CHECK-FP16: csetm {{.*}}, hi [all …]
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D | fp16_intrinsic_scalar_1op.ll | 26 ; CHECK-NEXT: csetm w0, eq 37 ; CHECK-NEXT: csetm w0, ge 48 ; CHECK-NEXT: csetm w0, gt 59 ; CHECK-NEXT: csetm w0, ls 70 ; CHECK-NEXT: csetm w0, mi
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D | fp16_intrinsic_scalar_2op.ll | 33 ; CHECK-NEXT: csetm w0, eq 44 ; CHECK-NEXT: csetm w0, ge 55 ; CHECK-NEXT: csetm w0, gt 66 ; CHECK-NEXT: csetm w0, ls 77 ; CHECK-NEXT: csetm w0, mi
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D | cond-sel.ll | 145 ; CHECK: csetm {{w[0-9]+}}, ls 234 ; CHECK: csetm {{w[0-9]+}}, eq 240 ; CHECK: csetm {{x[0-9]+}}, ls
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D | arm64-neon-select_cc.ll | 215 ; CHECK: csetm [[MASK:w[0-9]+]], ne
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/external/llvm/test/MC/AArch64/ |
D | basic-a64-diagnostics.s | 1385 csetm sp, ge 1387 csetm x6, nv
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D | basic-a64-instructions.s | 1406 csetm w20, ne 1407 csetm x30, ge
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
D | basic-a64-diagnostics.s | 1390 csetm sp, ge 1392 csetm x6, nv
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D | basic-a64-instructions.s | 1406 csetm w20, ne 1407 csetm x30, ge
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/external/v8/src/arm64/ |
D | macro-assembler-arm64-inl.h | 424 csetm(rd, cond); in Csetm()
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D | assembler-arm64.h | 1498 void csetm(const Register& rd, Condition cond);
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
D | basic-a64-instructions.txt | 948 # CHECK: csetm w20, ne 949 # CHECK: csetm x30, ge 950 # "cset w2, nv" and "csetm x3, al" are invalid aliases for these two 980 # CHECK: csetm w9, lt 983 # CHECK: csetm x9, lt
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | basic-a64-instructions.txt | 947 # CHECK: csetm w20, ne 948 # CHECK: csetm x30, ge 949 # "cset w2, nv" and "csetm x3, al" are invalid aliases for these two 979 # CHECK: csetm w9, lt 982 # CHECK: csetm x9, lt
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/external/vixl/test/test-trace-reference/ |
D | log-disasm | 70 0x~~~~~~~~~~~~~~~~ 5a9f93f5 csetm w21, hi 71 0x~~~~~~~~~~~~~~~~ 5a9f83f5 csetm w21, ls 72 0x~~~~~~~~~~~~~~~~ da9f13f6 csetm x22, eq 73 0x~~~~~~~~~~~~~~~~ da9f03f6 csetm x22, ne
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D | log-disasm-colour | 70 0x~~~~~~~~~~~~~~~~ 5a9f93f5 csetm w21, hi 71 0x~~~~~~~~~~~~~~~~ 5a9f83f5 csetm w21, ls 72 0x~~~~~~~~~~~~~~~~ da9f13f6 csetm x22, eq 73 0x~~~~~~~~~~~~~~~~ da9f03f6 csetm x22, ne
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D | log-cpufeatures-custom | 70 0x~~~~~~~~~~~~~~~~ 5a9f93f5 csetm w21, hi 71 0x~~~~~~~~~~~~~~~~ 5a9f83f5 csetm w21, ls 72 0x~~~~~~~~~~~~~~~~ da9f13f6 csetm x22, eq 73 0x~~~~~~~~~~~~~~~~ da9f03f6 csetm x22, ne
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D | log-cpufeatures | 70 0x~~~~~~~~~~~~~~~~ 5a9f93f5 csetm w21, hi 71 0x~~~~~~~~~~~~~~~~ 5a9f83f5 csetm w21, ls 72 0x~~~~~~~~~~~~~~~~ da9f13f6 csetm x22, eq 73 0x~~~~~~~~~~~~~~~~ da9f03f6 csetm x22, ne
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D | log-cpufeatures-colour | 70 0x~~~~~~~~~~~~~~~~ 5a9f93f5 csetm w21, hi 71 0x~~~~~~~~~~~~~~~~ 5a9f83f5 csetm w21, ls 72 0x~~~~~~~~~~~~~~~~ da9f13f6 csetm x22, eq 73 0x~~~~~~~~~~~~~~~~ da9f03f6 csetm x22, ne
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D | log-all | 210 0x~~~~~~~~~~~~~~~~ 5a9f93f5 csetm w21, hi 212 0x~~~~~~~~~~~~~~~~ 5a9f83f5 csetm w21, ls 214 0x~~~~~~~~~~~~~~~~ da9f13f6 csetm x22, eq 216 0x~~~~~~~~~~~~~~~~ da9f03f6 csetm x22, ne
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/external/vixl/test/aarch64/ |
D | test-trace-aarch64.cc | 123 __ csetm(w21, hi); in GenerateTestSequenceBase() local 124 __ csetm(w21, ls); in GenerateTestSequenceBase() local 125 __ csetm(x22, eq); in GenerateTestSequenceBase() local 126 __ csetm(x22, ne); in GenerateTestSequenceBase() local
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/external/vixl/src/aarch64/ |
D | macro-assembler-aarch64.cc | 1359 if (emit_code) masm->csetm(rd, cond); in CselSubHelperTwoOrderedImmediates()
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D | assembler-aarch64.h | 890 void csetm(const Register& rd, Condition cond);
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