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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleA57.td264 // +2cyc for branch forms
391 // For "Load, register offset, minus" we need +1cyc, +1I
425 // Load, immed pre-indexed (4 cyc for load result, 1 cyc for Base update)
429 // Load, register pre-indexed (4 cyc for load result, 2 cyc for Base update)
430 // (5 cyc load result for not-lsl2 scaled)
447 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm.
495 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm.
507 // 5cyc "I0/I1,L" for minus reg or scaled not plus lsl2
508 // otherwise 4cyc "L"
593 // TODO: no writeback latency defined in documentation (implemented as 1 cyc)
[all …]
DARMScheduleA57WriteRes.td15 // Latency: #cyc
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dcortex-a57-misched-alu.ll10 ; ALU, basic - 1 cyc I0/I1
15 ; ALU, shift by immed - 2 cyc M
20 ; ALU, shift by register, unconditional - 2 cyc M
25 ; ALU, shift by register, conditional - 2 cyc I0/I1
Dcortex-a57-misched-stm-wrback.ll3 ; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc
Dcortex-a57-misched-stm.ll3 ; N=3 STMIB should have latency 2cyc
Dcortex-a57-misched-basic.ll6 ; SDIV should be scheduled at the block's begin (20 cyc of independent M unit).
/external/mesa3d/src/mesa/sparc/
Dnorm.S82 fadds %f6, %f8, %f6 ! FGA Group 2cyc stall f6,f8 available
83 fadds %f6, %f10, %f6 ! FGA Group 4cyc stall f6,f10 available
209 fadds %f6, %f8, %f6 ! FGA Group 2cyc stall f6,f8 available
210 fadds %f6, %f10, %f6 ! FGA Group 4cyc stall f6,f10 available
513 fadds %f6, %f8, %f6 ! FGA Group 2cyc stall f6,f8 available
514 fadds %f6, %f10, %f6 ! FGA Group 4cyc stall f6,f10 available
/external/u-boot/drivers/i2c/
Di2c-uniphier-f.c29 u32 cyc; /* clock cycle control */ member
296 writel(clk_count, &regs->cyc); in uniphier_fi2c_set_bus_speed()
/external/slf4j/slf4j-site/src/site/pages/js/
Dprettify.js19 …ords:I,hashComments:true,cStyleComments:true}),["c","cc","cpp","cs","cxx","cyc"]);q(r({keywords:J,…
/external/deqp/framework/delibs/coding_guidelines/
Dprettify.js19 …ords:I,hashComments:true,cStyleComments:true}),["c","cc","cpp","cs","cxx","cyc"]);q(r({keywords:J,…
/external/doclava/res/assets/templates-sdk/assets/js/
Dprettify.js23 …words:F,hashComments:!0,cStyleComments:!0,types:K}),["c","cc","cpp","cxx","cyc","m"]);k(u({keyword…
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57WriteRes.td15 // Latency: #cyc
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedA57WriteRes.td15 // Latency: #cyc
DAArch64SchedFalkorDetails.td21 // Latency: #cyc
/external/hyphenation-patterns/en-GB/
Dhyph-en-gb.pat.txt1746 1cyc
/external/honggfuzz/examples/apache-httpd/corpus_http2/
D0bea195f554b90b58cd3c6c5862b30ac.0001cba4.honggfuzz.cov356 H��r0U�n���u:������cyc�A���z:�[�.�$�$�*��A���X^v�
/external/honggfuzz/examples/apache-httpd/corpus_http1/
D0bea195f554b90b58cd3c6c5862b30ac.0001cba4.honggfuzz.cov356 H��r0U�n���u:������cyc�A���z:�[�.�$�$�*��A���X^v�
/external/cldr/tools/java/org/unicode/cldr/util/data/transforms/
Dinternal_raw_IPA-old.txt47205 cyc saɪk
Dinternal_raw_IPA.txt39825 cyc %39178 saɪk