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Searched refs:ddr_phy (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/drivers/ram/rockchip/
Dsdram_rk322x.c91 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
109 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
112 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
115 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
121 void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq) in phy_dll_bypass_set() argument
125 setbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10); in phy_dll_bypass_set()
126 setbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10); in phy_dll_bypass_set()
127 setbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10); in phy_dll_bypass_set()
128 setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10); in phy_dll_bypass_set()
129 setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10); in phy_dll_bypass_set()
[all …]
/external/u-boot/arch/arm/mach-rockchip/rk3036/
Dsdram_rk3036.c368 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_pctrl_reset() local
386 clrsetbits_le32(&ddr_phy->ddrphy_reg1, in phy_pctrl_reset()
390 clrsetbits_le32(&ddr_phy->ddrphy_reg1, in phy_pctrl_reset()
399 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_dll_bypass_set() local
403 LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a); in phy_dll_bypass_set()
408 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6); in phy_dll_bypass_set()
414 &ddr_phy->ddrphy_reg9); in phy_dll_bypass_set()
417 LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a); in phy_dll_bypass_set()
423 &ddr_phy->ddrphy_reg6); in phy_dll_bypass_set()
429 &ddr_phy->ddrphy_reg9); in phy_dll_bypass_set()
[all …]
/external/u-boot/arch/arm/mach-imx/mx7/
Dddr.c28 struct ddr_phy *ddr_phy_regs_val, in mx7_dram_cfg()
34 struct ddr_phy *const ddr_phy_regs = in mx7_dram_cfg()
35 (struct ddr_phy *)DDRPHY_IPS_BASE_ADDR; in mx7_dram_cfg()
/external/u-boot/arch/arm/include/asm/arch-mx7/
Dmx7-ddr.h120 struct ddr_phy { struct
151 struct ddr_phy *ddr_phy_regs_val, argument
/external/u-boot/board/compulab/cl-som-imx7/
Dspl.c65 static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = {
/external/u-boot/drivers/clk/mvebu/
Darmada-37xx-periph.c200 CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, 1, div_table2, "TBG-A-S"),