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Searched refs:ddrc (Results 1 – 15 of 15) sorted by relevance

/external/u-boot/board/atmel/sama5d2_xplained/
Dsama5d2_xplained.c99 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
101 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
103 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
112 ddrc->rtr = 0x511; in ddrc_conf()
114 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddrc_conf()
123 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | in ddrc_conf()
128 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | in ddrc_conf()
/external/u-boot/board/atmel/sama5d27_som1_ek/
Dsama5d27_som1_ek.c98 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
100 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddrc_conf()
102 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
111 ddrc->rtr = 0x511; in ddrc_conf()
113 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | in ddrc_conf()
122 ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | in ddrc_conf()
127 ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | in ddrc_conf()
/external/u-boot/arch/arm/mach-imx/mx7/
Dddr.c27 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, in mx7_dram_cfg()
32 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in mx7_dram_cfg()
113 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in imx_ddr_size()
/external/u-boot/arch/arm/include/asm/arch-mx7/
Dmx7-ddr.h14 struct ddrc { struct
150 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
/external/u-boot/arch/arm/mach-zynq/
DMakefile11 obj-y += ddrc.o
/external/u-boot/drivers/ddr/fsl/
Dctrl_regs.c2370 struct ccsr_ddr __iomem *ddrc; in compute_fsl_memctl_config_regs() local
2374 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR; in compute_fsl_memctl_config_regs()
2378 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in compute_fsl_memctl_config_regs()
2383 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in compute_fsl_memctl_config_regs()
2388 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in compute_fsl_memctl_config_regs()
2623 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2631 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
/external/u-boot/board/compulab/cl-som-imx7/
Dspl.c37 static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {
/external/u-boot/board/hisilicon/hikey/
DREADME123 INFO: lpddr3_freq_init, set ddrc 533mhz
126 INFO: lpddr3_freq_init, set ddrc 800mhz
/external/u-boot/arch/arm/dts/
Dzynq-7000.dtsi158 compatible = "xlnx,zynq-ddrc-a05";
Dtegra20-tamonten.dtsi183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
Dtegra20-paz00.dts227 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
Dtegra20-ventana.dts245 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
Dtegra20-harmony.dts233 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
Dtegra20-seaboard.dts255 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
Dzynqmp.dtsi488 compatible = "xlnx,zynqmp-ddrc-2.40a";