| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_screen.c | 775 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; in radeonInitScreen2() local
785 depth_bits[0] = 0; in radeonInitScreen2()
787 depth_bits[1] = 16; in radeonInitScreen2()
789 depth_bits[2] = 24; in radeonInitScreen2()
791 depth_bits[3] = 24; in radeonInitScreen2()
800 depth_bits, in radeonInitScreen2()
802 ARRAY_SIZE(depth_bits), in radeonInitScreen2()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_screen.c | 775 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; in radeonInitScreen2() local
785 depth_bits[0] = 0; in radeonInitScreen2()
787 depth_bits[1] = 16; in radeonInitScreen2()
789 depth_bits[2] = 24; in radeonInitScreen2()
791 depth_bits[3] = 24; in radeonInitScreen2()
800 depth_bits, in radeonInitScreen2()
802 ARRAY_SIZE(depth_bits), in radeonInitScreen2()
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| /external/mesa3d/src/mesa/drivers/dri/common/ |
| D | utils.c | 159 const uint8_t * depth_bits, const uint8_t * stencil_bits, in driCreateConfigs() argument
242 (depth_bits[k] || stencil_bits[k])) { in driCreateConfigs()
249 if ((depth_bits[k] + stencil_bits[k] == 16) != in driCreateConfigs()
277 modes->depthBits = depth_bits[k]; in driCreateConfigs()
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| D | utils.h | 44 const uint8_t * depth_bits, const uint8_t * stencil_bits,
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| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| D | nouveau_screen.c | 57 const uint8_t depth_bits[] = { 0, 16, 24, 24 }; in nouveau_get_configs() local
75 depth_bits, stencil_bits, in nouveau_get_configs()
76 ARRAY_SIZE(depth_bits), in nouveau_get_configs()
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_screen.c | 1068 uint8_t depth_bits[4], stencil_bits[4]; in intel_screen_make_configs() local
1080 depth_bits[0] = 0; in intel_screen_make_configs()
1084 depth_bits[1] = 16; in intel_screen_make_configs()
1087 depth_bits[1] = 24; in intel_screen_make_configs()
1092 depth_bits, in intel_screen_make_configs()
1108 depth_bits[0] = 16; in intel_screen_make_configs()
1111 depth_bits[0] = 24; in intel_screen_make_configs()
1116 depth_bits, stencil_bits, 1, in intel_screen_make_configs()
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| /external/virglrenderer/src/gallium/auxiliary/util/ |
| D | u_format.c | 267 int depth_bits; in util_get_depth_format_mrd() local
269 depth_bits = desc->channel[depth_channel].size; in util_get_depth_format_mrd()
270 mrd = 1.0 / ((1ULL << depth_bits) - 1); in util_get_depth_format_mrd()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_screen.c | 2079 uint8_t depth_bits[4], stencil_bits[4]; in intel_screen_make_configs() local
2107 depth_bits[0] = 0; in intel_screen_make_configs()
2111 depth_bits[1] = 16; in intel_screen_make_configs()
2114 depth_bits[2] = 24; in intel_screen_make_configs()
2119 depth_bits[1] = 24; in intel_screen_make_configs()
2124 depth_bits, in intel_screen_make_configs()
2145 depth_bits[0] = 16; in intel_screen_make_configs()
2148 depth_bits[0] = 24; in intel_screen_make_configs()
2153 depth_bits, stencil_bits, 1, in intel_screen_make_configs()
2187 depth_bits[0] = 0; in intel_screen_make_configs()
[all …]
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| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_state.c | 208 unsigned depth_bits = in etna_set_framebuffer_state() local
233 cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f); in etna_set_framebuffer_state()
245 ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP); in etna_set_framebuffer_state()
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| /external/mesa3d/src/gallium/auxiliary/util/ |
| D | u_format.c | 287 int depth_bits; in util_get_depth_format_mrd() local
289 depth_bits = desc->channel[depth_channel].size; in util_get_depth_format_mrd()
290 mrd = 1.0 / ((1ULL << depth_bits) - 1); in util_get_depth_format_mrd()
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| /external/mesa3d/src/mesa/drivers/dri/swrast/ |
| D | swrast.c | 218 unsigned pixel_bits, unsigned depth_bits, in swrastFillInModes() argument
242 depth_bits_array[2] = depth_bits; in swrastFillInModes()
243 depth_bits_array[3] = depth_bits; in swrastFillInModes()
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