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Searched refs:dev_num (Results 1 – 25 of 73) sorted by relevance

123

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training.c90 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
91 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
93 static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
96 static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
99 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
101 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
207 static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id);
208 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
213 int ddr3_tip_tune_training_params(u32 dev_num, in ddr3_tip_tune_training_params() argument
258 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument
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Dddr3_training_leveling.c19 static int ddr3_tip_dynamic_write_leveling_seq(u32 dev_num);
20 static int ddr3_tip_dynamic_read_leveling_seq(u32 dev_num);
21 static int ddr3_tip_dynamic_per_bit_read_leveling_seq(u32 dev_num);
22 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id,
24 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
27 u32 ddr3_tip_max_cs_get(u32 dev_num) in ddr3_tip_max_cs_get() argument
32 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_max_cs_get()
35 CHECK_STATUS(ddr3_tip_get_first_active_if((u8)dev_num, in ddr3_tip_max_cs_get()
61 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 freq) in ddr3_tip_dynamic_read_leveling() argument
64 u32 max_cs = ddr3_tip_max_cs_get(dev_num); in ddr3_tip_dynamic_read_leveling()
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Dddr3_training_ip_prv_if.h23 typedef int (*HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR)(u8 dev_num, int enable);
25 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
28 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
31 u8 dev_num, enum hws_ddr_freq freq,
34 u8 dev_num, struct ddr3_device_info *info_ptr);
36 u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info);
38 u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
39 typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq);
41 u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
44 u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
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Dddr3_training_ip_flow.h126 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
129 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
132 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
134 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
137 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
139 int ddr3_tip_bus_read_modify_write(u32 dev_num,
144 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
147 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
151 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
153 int ddr3_tip_adjust_dqs(u32 dev_num);
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Dddr3_debug.c109 int ddr3_tip_reg_dump(u32 dev_num) in ddr3_tip_reg_dump() argument
113 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_reg_dump()
122 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_reg_dump()
140 (dev_num, if_id, in ddr3_tip_reg_dump()
151 (dev_num, if_id, in ddr3_tip_reg_dump()
167 int ddr3_tip_init_config_func(u32 dev_num, in ddr3_tip_init_config_func() argument
173 memcpy(&config_func_info[dev_num], config_func, in ddr3_tip_init_config_func()
183 u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) in hws_ddr3_tip_read_training_result() argument
207 int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr) in ddr3_tip_get_device_info() argument
209 if (config_func_info[dev_num].tip_get_device_info_func != NULL) { in ddr3_tip_get_device_info()
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Dddr3_training_ip_engine.c312 u32 *ddr3_tip_get_buf_ptr(u32 dev_num, enum hws_search_dir search, in ddr3_tip_get_buf_ptr() argument
334 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_ip_training() argument
355 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_ip_training()
377 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
381 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
386 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
390 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
396 ddr3_tip_load_pattern_to_odpg(dev_num, access_type, interface_num, in ddr3_tip_ip_training()
404 (dev_num, access_type, interface_num, direction, in ddr3_tip_ip_training()
412 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
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Dddr3_training_pbs.c33 int ddr3_tip_pbs(u32 dev_num, enum pbs_dir pbs_mode) in ddr3_tip_pbs() argument
51 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_pbs()
60 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs()
65 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs()
72 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS); in ddr3_tip_pbs()
75 ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_pbs()
100 (dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_pbs()
187 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs()
194 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs()
203 ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_pbs()
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Dddr3_training_hw_algo.c42 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) in ddr3_tip_write_additional_odt_setting() argument
51 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_write_additional_odt_setting()
53 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
56 CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
75 (dev_num, if_id, in ddr3_tip_write_additional_odt_setting()
99 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
103 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
111 int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4]) in get_valid_win_rx() argument
124 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id, in get_valid_win_rx()
145 int ddr3_tip_vref(u32 dev_num) in ddr3_tip_vref() argument
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Dddr3_training_centralization.c26 static int ddr3_tip_centralization(u32 dev_num, u32 mode);
31 int ddr3_tip_centralization_rx(u32 dev_num) in ddr3_tip_centralization_rx() argument
33 CHECK_STATUS(ddr3_tip_special_rx(dev_num)); in ddr3_tip_centralization_rx()
34 CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_RX)); in ddr3_tip_centralization_rx()
42 int ddr3_tip_centralization_tx(u32 dev_num) in ddr3_tip_centralization_tx() argument
44 CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_TX)); in ddr3_tip_centralization_tx()
52 static int ddr3_tip_centralization(u32 dev_num, u32 mode) in ddr3_tip_centralization() argument
63 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_centralization()
83 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_centralization()
87 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_centralization()
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Dddr3_training_ip_bist.h35 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
37 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
44 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
46 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
48 int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num,
50 int ddr3_tip_print_regs(u32 dev_num);
51 int ddr3_tip_reg_dump(u32 dev_num);
52 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
Dmv_ddr_plat.c182 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
188 static u32 ddr3_ctrl_get_junc_temp(u8 dev_num) in ddr3_ctrl_get_junc_temp() argument
222 static int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq, in ddr3_tip_a38x_get_freq_config() argument
362 static int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable) in ddr3_tip_a38x_select_ddr_controller() argument
386 static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq) in mv_ddr_sar_freq_get() argument
480 static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq) in ddr3_tip_a38x_get_medium_freq() argument
557 static int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr) in ddr3_tip_a38x_get_device_info() argument
637 static int mv_ddr_sw_db_init(u32 dev_num, u32 board_id) in mv_ddr_sw_db_init() argument
657 ddr3_tip_init_config_func(dev_num, &config_func); in mv_ddr_sw_db_init()
659 ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin); in mv_ddr_sw_db_init()
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Dddr3_init.h150 int ddr3_tip_enable_init_sequence(u32 dev_num);
164 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
165 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
168 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
169 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
170 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
172 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
174 int ddr3_tip_restore_dunit_regs(u32 dev_num);
182 int ddr3_tip_tune_training_params(u32 dev_num,
188 int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num);
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Dddr3_training_ip.h169 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
170 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
171 int hws_ddr3_tip_init_controller(u32 dev_num,
173 int hws_ddr3_tip_load_topology_map(u32 dev_num,
175 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
176 int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
177 int hws_ddr3_tip_read_training_result(u32 dev_num,
Dddr3_training_db.c609 u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index) in pattern_table_get_word() argument
793 void ddr3_tip_dev_attr_init(u32 dev_num) in ddr3_tip_dev_attr_init() argument
798 ddr_dev_attributes[dev_num][attr_id] = 0xFF; in ddr3_tip_dev_attr_init()
800 ddr_dev_attr_init_done[dev_num] = 1; in ddr3_tip_dev_attr_init()
803 u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id) in ddr3_tip_dev_attr_get() argument
805 if (ddr_dev_attr_init_done[dev_num] == 0) in ddr3_tip_dev_attr_get()
806 ddr3_tip_dev_attr_init(dev_num); in ddr3_tip_dev_attr_get()
808 return ddr_dev_attributes[dev_num][attr_id]; in ddr3_tip_dev_attr_get()
811 void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value) in ddr3_tip_dev_attr_set() argument
813 if (ddr_dev_attr_init_done[dev_num] == 0) in ddr3_tip_dev_attr_set()
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Dddr3_training_ip_centralization.h9 int ddr3_tip_centralization_tx(u32 dev_num);
10 int ddr3_tip_centralization_rx(u32 dev_num);
11 int ddr3_tip_print_centralization_result(u32 dev_num);
12 int ddr3_tip_special_rx(u32 dev_num);
Dddr3_training_ip_engine.h32 int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
39 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
40 int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
41 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
51 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
62 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
Dddr3_training_bist.c11 static int ddr3_tip_bist_operation(u32 dev_num,
19 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, in ddr3_tip_bist_activate() argument
73 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, in ddr3_tip_bist_read_result() argument
85 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
91 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
98 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
104 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
117 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, in hws_ddr3_run_bist() argument
129 ret = ddr3_tip_bist_activate(dev_num, pattern, in hws_ddr3_run_bist()
140 ret = ddr3_tip_bist_activate(dev_num, pattern, in hws_ddr3_run_bist()
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Dddr3_training_hw_algo.h9 int ddr3_tip_vref(u32 dev_num);
10 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
11 int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
Dddr3_training_leveling.h11 int ddr3_tip_print_wl_supp_result(u32 dev_num);
12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
14 u32 ddr3_tip_max_cs_get(u32 dev_num);
Dddr3_init.c29 static int mv_ddr_training_params_set(u8 dev_num);
181 static int mv_ddr_training_params_set(u8 dev_num) in mv_ddr_training_params_set() argument
190 (dev_num, tm->if_act_mask, in mv_ddr_training_params_set()
193 CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num)); in mv_ddr_training_params_set()
217 status = ddr3_tip_tune_training_params(dev_num, &params); in mv_ddr_training_params_set()
/external/linux-kselftest/tools/testing/selftests/zram/
Dzram_lib.sh49 for i in $(seq 0 $(($dev_num - 1))); do
70 echo "create '$dev_num' zram device(s)"
71 modprobe zram num_devices=$dev_num
79 if [ "$dev_num_created" -ne "$dev_num" ]; then
110 echo "$sys_path = '$max_streams' ($i/$dev_num)"
128 echo "$sys_path = '$alg' ($i/$dev_num)"
144 echo "$sys_path = '$ds' ($i/$dev_num)"
161 echo "$sys_path = '$ds' ($i/$dev_num)"
171 for i in $(seq 0 $(($dev_num - 1))); do
227 for i in $(seq 0 $(($dev_num - 1))); do
/external/ltp/testcases/kernel/device-drivers/zram/
Dzram_lib.sh37 for i in $(seq 0 $(($dev_num - 1))); do
48 tst_resm TINFO "create '$dev_num' zram device(s)"
49 modprobe zram num_devices=$dev_num || \
54 if [ "$dev_num_created" -ne "$dev_num" ]; then
84 tst_resm TINFO "$sys_path = '$max_streams' ($i/$dev_num)"
109 tst_resm TINFO "$sys_path = '$alg' ($i/$dev_num)"
125 tst_resm TINFO "$sys_path = '$ds' ($i/$dev_num)"
149 tst_resm TINFO "$sys_path = '$ds' ($i/$dev_num)"
160 for i in $(seq 0 $(($dev_num - 1))); do
219 for i in $(seq 0 $(($dev_num - 1))); do
/external/u-boot/include/
Dnetdev.h30 int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
33 int cs8900_initialize(u8 dev_num, int base_addr);
41 int ep93xx_eth_initialize(u8 dev_num, int base_addr);
43 int ethoc_initialize(u8 dev_num, int base_addr);
51 int ks8851_mll_initialize(u8 dev_num, int base_addr);
52 int lan91c96_initialize(u8 dev_num, int base_addr);
70 int smc91111_initialize(u8 dev_num, int base_addr);
71 int smc911x_initialize(u8 dev_num, int base_addr);
/external/u-boot/cmd/
Dandroid_cmds.c31 int dev_num; in part_get_info_by_dev_and_name() local
37 dev_num = simple_strtoul(dev_part_str, &ep, 16); in part_get_info_by_dev_and_name()
44 *dev_desc = blk_get_dev(dev_iface, dev_num); in part_get_info_by_dev_and_name()
46 printf("Could not find %s %d\n", dev_iface, dev_num); in part_get_info_by_dev_and_name()
/external/u-boot/drivers/dfu/
Ddfu_mmc.c29 mmc = find_mmc_device(dfu->data.mmc.dev_num); in mmc_block_op()
31 pr_err("Device MMC %d - not found!", dfu->data.mmc.dev_num); in mmc_block_op()
53 dfu->data.mmc.dev_num, in mmc_block_op()
61 dfu->data.mmc.dev_num, blk_start, blk_count, buf); in mmc_block_op()
78 dfu->data.mmc.dev_num, in mmc_block_op()
85 dfu->data.mmc.dev_num, in mmc_block_op()
309 dfu->data.mmc.dev_num = simple_strtoul(devstr, NULL, 10); in dfu_fill_entity_mmc()
327 mmc = find_mmc_device(dfu->data.mmc.dev_num); in dfu_fill_entity_mmc()
330 dfu->data.mmc.dev_num); in dfu_fill_entity_mmc()

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