Searched refs:dmfc1 (Results 1 – 25 of 73) sorted by relevance
123
| /external/llvm/test/CodeGen/Mips/ |
| D | fpxx.ll | 208 ; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
211 ; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
215 ; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
218 ; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
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| D | mips64-libcall.ll | 9 ; HARD-NOT: dmfc1 $4
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| D | fcopysign-f32-f64.ll | 45 ; 64-DAG: dmfc1 $[[R0:[0-9]+]], ${{.*}}
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | fpxx.ll | 208 ; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
211 ; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
215 ; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
218 ; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
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| D | mips64-libcall.ll | 9 ; HARD-NOT: dmfc1 $4
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| D | fcopysign-f32-f64.ll | 41 ; 64: dmfc1 $[[R0:[0-9]+]], ${{.*}}
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| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.cc | 1405 dmfc1(scratch, fd); in Usdc1()
2116 dmfc1(scratch1, fs); in Neg_d()
2147 dmfc1(t8, fs); in Cvt_d_ul()
2201 dmfc1(t8, fs); in Cvt_s_ul()
2259 dmfc1(t8, fs); in Trunc_l_ud()
2419 dmfc1(rd, scratch); in Trunc_ul_d()
2426 dmfc1(rd, scratch); in Trunc_ul_d()
2436 dmfc1(result, scratch); in Trunc_ul_d()
2478 dmfc1(rd, scratch); in Trunc_ul_s()
2485 dmfc1(rd, scratch); in Trunc_ul_s()
[all …]
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| /external/v8/src/wasm/baseline/mips64/ |
| D | liftoff-assembler-mips64.h | 836 dmfc1(dst.gp(), kScratchDoubleReg); in FP_BINOP()
868 dmfc1(dst.gp(), kScratchDoubleReg); in FP_BINOP()
892 dmfc1(dst.gp(), src.fp()); in FP_BINOP()
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| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips3.s | 22 …dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
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| D | invalid-mips5.s | 22 …dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
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| D | invalid-mips4.s | 22 …dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips3.s | 22 …dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
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| D | invalid-mips4.s | 22 …dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-el.txt | 86 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
231 0x00 0x70 0x22 0x44 # CHECK: dmfc1 $2, $f14
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 38 class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
163 class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
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| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-el.txt | 86 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
227 0x00 0x70 0x22 0x44 # CHECK: dmfc1 $2, $f14
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| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-mips64r2-el.txt | 92 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
248 0x00 0x70 0x22 0x44 # CHECK: dmfc1 $2, $f14
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| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | valid.s | 207 dmfc1 $9, $f4 # CHECK: dmfc1 $9, $f4 # encoding: [0x55,0x24,0x24,0x3b]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-mips64r2-el.txt | 93 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
253 0x00 0x70 0x22 0x44 # CHECK: dmfc1 $2, $f14
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/ |
| D | invalid-mips3.s | 26 …dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| D | invalid-mips5.s | 24 …dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| D | invalid-mips4.s | 24 …dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| /external/llvm/test/MC/Mips/mips1/ |
| D | invalid-mips3.s | 26 …dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| D | invalid-mips5.s | 24 …dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| /external/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 76 dmfc1 $12,$f13
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