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Searched refs:dpll_params (Results 1 – 25 of 32) sorted by relevance

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/external/u-boot/arch/arm/include/asm/arch-am33xx/
Dclock.h80 struct dpll_params { struct
107 extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS]; argument
108 extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
109 extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
110 extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];
111 extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];
112 extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
116 const struct dpll_params *get_dpll_mpu_params(void);
117 const struct dpll_params *get_dpll_core_params(void);
118 const struct dpll_params *get_dpll_per_params(void);
[all …]
Dclocks_am33xx.h32 extern const struct dpll_params dpll_core_opp100;
33 extern struct dpll_params dpll_mpu_opp100;
/external/u-boot/board/compulab/cm_t43/
Dspl.c16 const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
17 const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
18 const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
19 const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 };
84 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
89 const struct dpll_params *get_dpll_mpu_params(void) in get_dpll_mpu_params()
94 const struct dpll_params *get_dpll_core_params(void) in get_dpll_core_params()
99 const struct dpll_params *get_dpll_per_params(void) in get_dpll_per_params()
/external/u-boot/arch/arm/mach-omap2/am33xx/
Dclock_am33xx.c61 struct dpll_params dpll_mpu_opp100 = {
63 const struct dpll_params dpll_core_opp100 = {
66 const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
101 const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ] = {
108 const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = {
115 const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
122 const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
129 const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
136 __weak const struct dpll_params *get_dpll_mpu_params(void) in get_dpll_mpu_params()
141 const struct dpll_params *get_dpll_core_params(void) in get_dpll_core_params()
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Dclock.c18 const struct dpll_params *params) in setup_post_dividers()
73 const struct dpll_params *params) in do_setup_dpll()
102 const struct dpll_params *params; in setup_dplls()
249 const struct dpll_params *params; in rtc_only_prcm_init()
Dchilisom.c160 const struct dpll_params dpll_ddr_chilisom = {
163 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
/external/u-boot/arch/arm/mach-omap2/omap5/
Dhw_data.c31 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
42 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
52 static const struct dpll_params
63 static const struct dpll_params
74 static const struct dpll_params
85 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
95 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
105 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
115 static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
125 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
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/external/u-boot/arch/arm/mach-omap2/omap4/
Dhw_data.c39 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
54 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
68 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
80 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
91 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
102 static const struct dpll_params
113 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
123 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
135 static const struct dpll_params
147 static const struct dpll_params abe_dpll_params_32k_196608khz = {
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/external/u-boot/arch/arm/mach-omap2/
Dpipe3-phy.c108 struct pipe3_dpll_params *dpll_params; in omap_pipe3_dpll_program() local
110 dpll_params = omap_pipe3_get_dpll_params(phy); in omap_pipe3_dpll_program()
111 if (!dpll_params) { in omap_pipe3_dpll_program()
118 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_pipe3_dpll_program()
123 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; in omap_pipe3_dpll_program()
128 val |= dpll_params->m << PLL_REGM_SHIFT; in omap_pipe3_dpll_program()
133 val |= dpll_params->mf << PLL_REGM_F_SHIFT; in omap_pipe3_dpll_program()
138 val |= dpll_params->sd << PLL_SD_SHIFT; in omap_pipe3_dpll_program()
Dclocks-common.c73 void setup_post_dividers(u32 const base, const struct dpll_params *params) in setup_post_dividers()
148 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data) in get_mpu_dpll_params()
154 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data) in get_core_dpll_params()
160 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data) in get_per_dpll_params()
166 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data) in get_iva_dpll_params()
172 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data) in get_usb_dpll_params()
178 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) in get_abe_dpll_params()
188 static const struct dpll_params *get_ddr_dpll_params in get_ddr_dpll_params()
199 static const struct dpll_params *get_gmac_dpll_params in get_gmac_dpll_params()
210 static void do_setup_dpll(u32 const base, const struct dpll_params *params, in do_setup_dpll()
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/external/u-boot/drivers/usb/phy/
Domap_usb_phy.c80 struct usb3_dpll_params *dpll_params; in omap_usb_dpll_lock() local
83 dpll_params = omap_usb3_get_dpll_params(); in omap_usb_dpll_lock()
84 if (!dpll_params) in omap_usb_dpll_lock()
89 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_usb_dpll_lock()
94 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; in omap_usb_dpll_lock()
99 val |= dpll_params->m << PLL_REGM_SHIFT; in omap_usb_dpll_lock()
104 val |= dpll_params->mf << PLL_REGM_F_SHIFT; in omap_usb_dpll_lock()
109 val |= dpll_params->sd << PLL_SD_SHIFT; in omap_usb_dpll_lock()
/external/u-boot/drivers/usb/dwc3/
Dti_usb_phy.c149 struct usb3_dpll_params *dpll_params; in ti_usb3_dpll_program() local
154 dpll_params = ti_usb3_get_dpll_params(phy); in ti_usb3_dpll_program()
155 if (!dpll_params) in ti_usb3_dpll_program()
160 val |= dpll_params->n << PLL_REGN_SHIFT; in ti_usb3_dpll_program()
165 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; in ti_usb3_dpll_program()
170 val |= dpll_params->m << PLL_REGM_SHIFT; in ti_usb3_dpll_program()
175 val |= dpll_params->mf << PLL_REGM_F_SHIFT; in ti_usb3_dpll_program()
180 val |= dpll_params->sd << PLL_SD_SHIFT; in ti_usb3_dpll_program()
/external/u-boot/drivers/phy/
Dti-pipe3-phy.c130 struct pipe3_dpll_params *dpll_params; in omap_pipe3_dpll_program() local
132 dpll_params = omap_pipe3_get_dpll_params(pipe3); in omap_pipe3_dpll_program()
133 if (!dpll_params) { in omap_pipe3_dpll_program()
140 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_pipe3_dpll_program()
145 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; in omap_pipe3_dpll_program()
150 val |= dpll_params->m << PLL_REGM_SHIFT; in omap_pipe3_dpll_program()
155 val |= dpll_params->mf << PLL_REGM_F_SHIFT; in omap_pipe3_dpll_program()
160 val |= dpll_params->sd << PLL_SD_SHIFT; in omap_pipe3_dpll_program()
/external/u-boot/arch/arm/include/asm/
Domap_common.h487 struct dpll_params { struct
522 const struct dpll_params *mpu; argument
523 const struct dpll_params *core;
524 const struct dpll_params *per;
525 const struct dpll_params *abe;
526 const struct dpll_params *iva;
527 const struct dpll_params *usb;
528 const struct dpll_params *ddr;
529 const struct dpll_params *gmac;
615 const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
[all …]
/external/u-boot/board/ti/am43xx/
Dboard.c54 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
89 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
96 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
103 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
110 const struct dpll_params gp_evm_dpll_ddr = {
113 static const struct dpll_params idk_dpll_ddr = {
320 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
363 const struct dpll_params *get_dpll_mpu_params(void) in get_dpll_mpu_params()
371 const struct dpll_params *get_dpll_core_params(void) in get_dpll_core_params()
378 const struct dpll_params *get_dpll_per_params(void) in get_dpll_per_params()
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/external/u-boot/board/silica/pengwyn/
Dboard.c71 const struct dpll_params dpll_ddr_266 = {
73 const struct dpll_params dpll_ddr_303 = {
75 const struct dpll_params dpll_ddr_400 = {
99 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
/external/u-boot/board/eets/pdu001/
Dboard.c185 const struct dpll_params dpll_ddr = {
187 const struct dpll_params dpll_ddr_evm_sk = {
189 const struct dpll_params dpll_ddr_bone_black = {
209 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
/external/u-boot/board/gumstix/pepper/
Dboard.c65 const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
98 const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
122 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
144 const struct dpll_params *dpll = get_dpll_ddr_params(); in sdram_init()
/external/u-boot/board/birdland/bav335x/
Dboard.c174 const struct dpll_params dpll_ddr = {
176 const struct dpll_params dpll_ddr_evm_sk = {
178 const struct dpll_params dpll_ddr_bone_black = {
232 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
/external/u-boot/board/vscom/baltos/
Dboard.c165 const struct dpll_params dpll_ddr = {
167 const struct dpll_params dpll_ddr_evm_sk = {
169 const struct dpll_params dpll_ddr_baltos = {
223 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
/external/u-boot/board/compulab/cm_t335/
Dspl.c59 const struct dpll_params dpll_ddr = {
77 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
/external/u-boot/board/BuR/brppt1/
Dboard.c93 static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
132 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
/external/u-boot/board/siemens/common/
Dboard.c101 const struct dpll_params dpll_ddr = {
104 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
/external/u-boot/board/phytec/pcm051/
Dboard.c44 const struct dpll_params dpll_ddr = {
47 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()
/external/u-boot/board/BuR/brxre1/
Dboard.c88 const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
138 const struct dpll_params *get_dpll_ddr_params(void) in get_dpll_ddr_params()

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